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| 1 1006d?avr?07/03 features utilizes the avr ? risc architecture high-performance and low-power 8-bit risc architecture ? 90 powerful instructions ? most single clock cycle execution ? 32 x 8 general purpose working registers ? up to 8 mips throughput at 8 mhz nonvolatile program and data memory ? 1k byte of flash program memory in-system programmable (attiny12) endurance: 1,000 write/erase cycles (attiny11/12) ? 64 bytes of in-system programmable eeprom data memory for attiny12 endurance: 100,000 write/erase cycles ? programming lock for flash program and eeprom data security peripheral features ? interrupt and wake-up on pin change ? one 8-bit timer/counter with separate prescaler ? on-chip analog comparator ? programmable watchdog timer with on-chip oscillator special microcontroller features ? low-power idle and power-down modes ? external and internal interrupt sources ? in-system programmable via spi port (attiny12) ? enhanced power-on reset circuit (attiny12) ? internal calibrated rc oscillator (attiny12) specification ? low-power, high-speed cmos process technology ? fully static operation power consumption at 4 mhz, 3v, 25c ? active: 2.2 ma ? idle mode: 0.5 ma ? power-down mode: <1 a packages ? 8-pin pdip and soic operating voltages ? 1.8 - 5.5v for attiny12v-1 ? 2.7 - 5.5v for attiny11l-2 and attiny12l-4 ? 4.0 - 5.5v for attiny11-6 and attiny12-8 speed grades ? 0 - 1.2 mhz (attiny12v-1) ? 0 - 2 mhz (attiny11l-2) ? 0 - 4 mhz (attiny12l-4) ? 0 - 6 mhz (attiny11-6) ? 0 - 8 mhz (attiny12-8) pin configuration 1 2 3 4 8 7 6 5 (reset) pb5 (xtal1) pb3 (xtal2) pb4 gnd vcc pb2 (t0) pb1 (int0/ain1) pb0 (ain0) attiny11 pdip/soic 1 2 3 4 8 7 6 5 (reset) pb5 (xtal1) pb3 (xtal2) pb4 gnd vcc pb2 (sck/t0) pb1 (miso/int0/ain1) pb0 (mosi/ain0) attiny12 pdip/soic 8-bit microcontroller with 1k byte flash attiny11 attiny12 rev. 1006d?avr?07/03
2 attiny11/12 1006d?avr?07/03 description the attiny11/12 is a low-power cmos 8-bit microcontroller based on the avr risc architecture. by executing powerful instructions in a single clock cycle, the attiny11/12 achieves throughputs approaching 1 mips per mhz, allowing the system designer to optimize power consumption versus processing speed. the avr core combines a rich instruction set with 32 general-purpose working regis- ters. all the 32 registers are directly connected to the arithmetic logic unit (alu), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. the resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional cisc microcontrollers. attiny11 block diagram the attiny11 provides the following features: 1k bytes of flash, up to five general-pur- pose i/o lines, one input line, 32 general-purpose working registers, an 8-bit timer/counter, internal and external in terrupts, programmable watchdog timer with internal oscillator, and two software-selectable power-saving modes. the idle mode stops the cpu while allowing the timer/count ers and interrupt system to continue func- tioning. the power-down mode saves the register contents but freezes the oscillator, disabling all other chip functions until the next interrupt or hardware reset. the wake-up or interrupt on pin change features enable the attiny11 to be highly responsive to exter- nal events, still featuring the lowest power consumption while in the power-down modes. the device is manufactured using atmel?s high-density nonvolatile memory technology. by combining an risc 8-bit cpu with flash on a monolithic chip, the atmel attiny11 is a powerful microcontroller that provides a highly-flexible and cost-effective solution to many embedded control applications. the attiny11 avr is supported with a full suite of program and system development tools including: macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits. table 1. parts description device flash eeprom register voltage range frequency attiny11l 1k - 32 2.7 - 5.5v 0-2 mhz attiny11 1k - 32 4.0 - 5.5v 0-6 mhz attiny12v 1k 64 b 32 1.8 - 5.5v 0-1.2 mhz attiny12l 1k 64 b 32 2.7 - 5.5v 0-4 mhz attiny12 1k 64 b 32 4.0 - 5.5v 0-8 mhz 3 attiny11/12 1006d?avr?07/03 figure 1. the attiny11 block diagram program counter internal oscillator watchdog timer stack pointer program flash hardware stack mcu control register general- purpose registers instruction register timer/ counter instruction decoder data dir. reg. portb data register portb programming logic oscillators timing and control interrupt unit mcu status register status register alu portb drivers pb0-pb5 vcc gnd control lines + - analog comp arator 8-bit data bus z 4 attiny11/12 1006d?avr?07/03 attiny12 block diagram figure 2. the attiny12 block diagram the attiny12 provides the following features: 1k bytes of flash, 64 bytes eeprom, up to six general-purpose i/o lines, 32 general-purpose working registers, an 8-bit timer/counter, internal and external in terrupts, programmable watchdog timer with internal oscillator, and two software-selectable power-saving modes. the idle mode stops the cpu while allowing the timer/count ers and interrupt system to continue func- tioning. the power-down mode saves the register contents but freezes the oscillator, disabling all other chip functions until the next interrupt or hardware reset. the wake-up or interrupt on pin change features enable the attiny12 to be highly responsive to exter- nal events, still featuring the lowest power consumption while in the power-down modes. the device is manufactured using atmel?s high-density nonvolatile memory technology. by combining an risc 8-bit cpu with flash on a monolithic chip, the atmel attiny12 is a powerful microcontroller that provides a highly-flexible and cost-effective solution to many embedded control applications. program counter internal oscillator watchdog timer stack pointer program flash hardware stack mcu control register general- purpose registers instruction register timer/ counter instruction decoder data dir. reg. portb data register portb programming logic oscillators timing and control interrupt unit mcu status register status register alu portb drivers pb0-pb5 vcc gnd control lines + - analog comp arator z 8-bit data bus eeprom spi internal oscillator calibrated 5 attiny11/12 1006d?avr?07/03 the attiny12 avr is supported with a full suite of program and system development tools including: macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits. pin descriptions vcc supply voltage pin. gnd ground pin. port b (pb5..pb0) port b is a 6-bit i/o port. pb4..0 are i/o pins that can provide internal pull-ups (selected for each bit). on attiny11, pb5 is input only. on attiny12, pb5 is input or open-drain output. the port pins are tri-stated when a reset condition becomes active, even if the clock is not running. the use of pins pb5..3 as input or i/o pins is limited, depending on reset and clock settings, as shown below. notes: 1. ?used? means the pin is used for reset or clock purposes. 2. ?-? means the pin function is unaffected by the option. 3. input means the pin is a port input pin. 4. on attiny11, pb5 is input only. on attiny12, pb5 is input or open-drain output. 5. i/o means the pin is a port input/output pin. xtal1 input to the inverting oscillator amplifier and input to the internal clock operating circuit. xtal2 output from the inverting oscillator amplifier. reset reset input. an external reset is generated by a low level on the reset pin. reset pulses longer than 50 ns will generate a reset, even if the clock is not running. shorter pulses are not guaranteed to generate a reset. clock options the device has the following clock source options, selectable by flash fuse bits as shown: table 2. pb5..pb3 functionality vs. device clocking options device clocking option pb5 pb4 pb3 external reset enabled used (1) - (2) - external reset disabled input (3) /i/o (4) -- external crystal - used used external low-frequency crystal - used used external ceramic resonator - used used external rc oscillator - i/o (5) used external clock - i/o used internal rc oscillator - i/o i/o table 3. device clocking options select device clocking option attiny11 cksel2..0 attiny12 cksel3..0 external crystal/ceramic resonator 111 1111 - 1010 external low-frequency crystal 110 1001 - 1000 external rc oscillator 101 0111 - 0101 6 attiny11/12 1006d?avr?07/03 note: ?1? means unprogrammed, ?0? means programmed. the various choices for each clocking option give different start-up times as shown in table 7 on page 18 and table 9 on page 20. internal rc oscillator the internal rc oscillator option is an on-chip oscillator running at a fixed frequency of 1 mhz in attiny11 and 1.2 mhz in attiny12. if selected, the device can operate with no external components. the device is shipped with this option selected. on attiny11, the watchdog oscillator is used as a clock, while attiny12 uses a separate calibrated oscillator. crystal oscillator xtal1 and xtal2 are input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in figure 3. either a quartz crystal or a ceramic resonator may be used. maximum frequency for crystal and resona- tors is 4 mhz. minimum voltage for running on a low-frequency crystal is 2.5v. figure 3. oscillator connections note: when using the mcu oscillator as a clock for an external device, an hc buffer should be connected as indicated in the figure. external clock to drive the device from an external clock source, xtal1 should be driven as shown in figure 4. figure 4. external clock drive configuration internal rc oscillator 100 0100 - 0010 external clock 000 0001 - 0000 reserved other options - table 3. device clocking options select (continued) device clocking option attiny11 cksel2..0 attiny12 cksel3..0 xtal2 xtal1 gnd c2 c1 max 1 hc buffer hc pb4 (xtal2) xtal1 gnd external oscillator signal 7 attiny11/12 1006d?avr?07/03 external rc oscillator for timing insensitive applications, the external rc configuration shown in figure 5 can be used. for details on how to choose r and c, see table 29 on page 59. the external rc oscillator is sensitive to noise from neighboring pins, and to avoid problems, pb5 (reset ) should be used as an output or reset pin, and pb4 should be used as an out- put pin. figure 5. external rc configuration pb4 (xtal2) xtal1 gnd c r v cc 8 attiny11/12 1006d?avr?07/03 architectural overview the fast-access register file concept contains 32 x 8-bit general-purpose working regis- ters with a single-clock-cycle access time. this means that during one single clock cycle, one alu (arithmetic logic unit) operation is executed. two operands are output from the register file, the operation is executed, and the result is stored back in the reg- ister file ? in one clock cycle. two of the 32 registers can be used as a 16-bit pointer for indirect memory access. this pointer is called the z-pointer, and can addre ss the register file and the flash program memory. the alu supports arithmetic and logic functions between registers or between a con- stant and a register. single-register operations are also executed in the alu. figure 2 shows the attiny11/12 avr risc microcontroller architecture. the avr uses a har- vard architecture concept with separate memories and buses for program and data memories. the program memory is accessed with a two-stage pipelining. while one instruction is being executed, the next instruction is pre-fetched from the program mem- ory. this concept enables instructions to be executed in every clock cycle. the program memory is reprogrammable flash memory. with the relative jump and relative call instructions, the whole 512 address space is directly accessed. all avr instructions have a single 16-bit word format, meaning that every program memory address contains a single 16-bit instruction. during interrupts and subroutine calls, the return address program counter (pc) is stored on the stack. the stack is a 3-level-deep hardware stack dedicated for subrou- tines and interrupts. the i/o memory space contains 64 addresses for cpu peripheral functions as control registers, timer/counters, and other i/o functions. the memory spaces in the avr archi- tecture are all linear and regular memory maps. 9 attiny11/12 1006d?avr?07/03 figure 6. the attiny11/12 avr risc architecture a flexible interrupt module has its control registers in the i/o space with an additional global interrupt enable bit in the status register. all the different interrupts have a sepa- rate interrupt vector in the interrupt vector table at the beginning of the program memory. the different interrupts have priority in accordance with their interrupt vector position. the lower the interrupt vector address, the higher the priority. general-purpose register file figure 7 shows the structure of the 32 general-purpose registers in the cpu. figure 7. avr cpu general-purpose working registers all the register operating instructions in the instruction set have direct- and single-cycle access to all registers. the only exception is the five constant arithmetic and logic instructions sbci, subi, cpi, andi, and ori between a constant and a register and the ldi instruction for load-immediate constant data. these instructions apply to the second half of the registers in the register file ? r16..r31. the general sbc, sub, cp, and, 512 x 16 program flash instruction register instruction decoder program counter control lines 32 x 8 general- purpose registers alu direct addressing status and test control registers interrupt unit 8-bit timer/counter watchdog timer analog comparator 6 i/o lines 8-bit data bus spi unit (attiny12 only) 64 x 8 eeprom (attiny12 only) 70 r0 r1 r2 general- ? purpose ? working r28 registers r29 r30 (z-register low byte) r31 (z-register high byte) 10 attiny11/12 1006d?avr?07/03 or and all other operations between two registers or on a single register apply to the entire register file. registers 30 and 31 form a 16-bit pointer (the z-pointer) which is used for indirect flash memory and register file access. when the register file is accessed, the contents of r31 are discarded by the cpu. alu ? arithmetic logic unit the high-performance avr alu operates in direct connection with all the 32 general- purpose working registers. within a single clock cycle, alu operations between regis- ters in the register file are executed. the alu operations are divided into three main categories ? arithmetic, logic and bit-functions. some microcontrollers in the avr prod- uct family feature a hardware multiplier in the arithmetic part of the alu. flash program memory the attiny11/12 contains 1k bytes on-chip flash memory for program storage. since all instructions are single 16-bit words, the flash is organized as 512 x 16 words. the flash memory has an endurance of at least 1000 write/erase cycles. the attiny11/12 program counter is 9 bits wide, thus addressing the 512 words flash program memory. see page 46 for a detailed description on flash memory programming. program and data addressing modes the attiny11/12 avr risc microcontroller supports powerful and efficient addressing modes. this section describes the different addressing modes supported in the attiny11/12. in the figures, op means the operation code part of the instruction word. to simplify, not all figures show the exact location of the addressing bits. register direct, single register rd figure 8. direct single-register addressing the operand is contained in register d (rd). 11 attiny11/12 1006d?avr?07/03 register indirect figure 9. indirect register addressing the register accessed is the one pointed to by the z-register (r31, r30). register direct, two registers rd and rr figure 10. direct register addressing, two registers operands are contained in register r (rr) and d (rd). the result is stored in register d (rd). i/o direct figure 11. i/o direct addressing operand address is contained in 6 bits of the instruction word. n is the destination or source register address. register file 0 31 30 z-register 12 attiny11/12 1006d?avr?07/03 relative program addressing, rjmp and rcall figure 12. relative program memory addressing program execution continues at address pc + k + 1. the relative address k is -2048 to 2047. constant addressing using the lpm instruction figure 13. code memory constant addressing constant byte address is specified by the z-register contents. the 15 msbs select word address (0 - 511), the lsb selects low byte if cleared (lsb = 0) or high byte if set (lsb = 1). subroutine and interrupt hardware stack the attiny11/12 uses a 3-level-deep hardware stack for subroutines and interrupts. the hardware stack is 9 bits wide and stores the program counter (pc) return address while subroutines and interrupts are executed. rcall instructions and interrupts push the pc return address onto stack level 0, and the data in the other stack levels 1-2 are pushed one level deeper in the stack. when a ret or reti instruction is executed the returning pc is fetched from stack level 0, and the data in the other stack levels 1-2 are popped one level in the stack. if more than three subsequent subroutine calls or interrupts are executed, the first val- ues written to the stack are overwritten. pu shing four return addresses a1, a2, a3, and a4, followed by four subroutine or interrupt returns, will pop a4, a3, a2, and once more a2 from the hardware stack. +1 $1ff $000 program memory 15 1 0 z-register 13 attiny11/12 1006d?avr?07/03 eeprom data memory the attiny12 contains 64 bytes of data eeprom memory. it is organized as a separate data space, in which single bytes can be read and written. the eeprom has an endur- ance of at least 100,000 write/erase cycles. the access between the eeprom and the cpu is described on page 38, specifying the eeprom address register, the eeprom data register, and the eeprom control register. for spi data downloading, see ?memory programming? on page 46 for a detailed description. memory access and instruction execution timing this section describes the general access timing concepts for instruction execution and internal memory access. the avr cpu is driven by the system clock ?, directly generated from the external clock crystal for the chip. no internal clock division is used. figure 14 shows the parallel instruction fetches and instruction executions enabled by the harvard architecture and the fast-access register file concept. this is the basic pipe- lining concept to obtain up to 1 mips per mhz with the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit. figure 14. the parallel instruction fetches and instruction executions figure 15 shows the internal timing concept fo r the register file. in a single clock cycle, an alu operation using two register operands is executed and the result is stored back to the destination register. figure 15. single-cycle alu operation system clock ? 1st instruction fetch 1st instruction execute 2nd instruction fetch 2nd instruction execute 3rd instruction fetch 3rd instruction execute 4th instruction fetch t1 t2 t3 t4 system clock ? total execution time register operands fetch alu operation execute result write back t1 t2 t3 t4 14 attiny11/12 1006d?avr?07/03 i/o memory the i/o space definition of the attiny11/12 is shown in the following table: note: reserved and unused locations are not shown in the table. all the different attiny11/12 i/o and peripherals are placed in the i/o space. the differ- ent i/o locations are accessed by the in and out instructions transferring data between the 32 general-purpose working registers and t he i/o space. i/o registers within the address range $00 - $1f are directly bit-accessible using the sbi and cbi instructions. in these registers, the value of single bits can be checked by using the sbis and sbic instructions. refer to the instruction set summary for more details. for compatibility with future devices, reserved bits should be written to zero if accessed. reserved i/o memory addressed should never be written. the different i/o and peripherals control registers are explained in the following sections. status register ? sreg the avr status register (sreg) at i/o space location $3f is defined as: bit 7 - i: global interrupt enable the global interrupt enable bit must be set (one) for the interrupts to be enabled. the individual interrupt enable control is then performed in separate control registers. if the table 4. attiny11/12 i/o space address hex name device function $3f sreg attiny11/12 status register $3b gimsk attiny11/12 general interrupt mask register $3a gifr attiny11/12 general interrupt flag register $39 timsk attiny11/12 timer/counter interrupt mask register $38 tifr attiny11/12 timer/counter interrupt flag register $35 mcucr attiny11/12 mcu control register $34 mcusr attiny11/12 mcu status register $33 tccr0 attiny11/12 timer/counter0 control register $32 tcnt0 attiny11/12 timer/counter0 (8-bit) $31 osccal attiny12 oscillator calibration register $21 wdtcr attiny11/12 watchdog timer control register $1e eear attiny12 eeprom address register $1d eedr attiny12 eeprom data register $1c eecr attiny12 eeprom control register $18 portb attiny11/12 data register, port b $17 ddrb attiny11/12 data direction register, port b $16 pinb attiny11/12 input pins, port b $08 acsr attiny11/12 analog comparator control and status register bit 76543210 $3f ithsvnzcsreg read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 15 attiny11/12 1006d?avr?07/03 global interrupt enable register is cleared (zero), none of the interrupts are enabled inde- pendent of the individual interrupt enable settings. the i-bit is cleared by hardware after an interrupt has occurred, and is set by the reti instruction to enable subsequent interrupts. bit 6 - t: bit copy storage the bit copy instructions bld (bit load) and bst (bit store) use the t-bit as source and destination for the operated bit. a bit from a register in the register file can be copied into t by the bst instruction, and a bit in t can be copied into a bit in a register in the register file by the bld instruction. bit 5 - h: half carry flag the half carry flag h indicates a half-carry in some arithmetic operations. see the instruction set description for detailed information. bit 4 - s: sign bit, s = n v the s-bit is always an exclusive or between the negative flag n and the two?s comple- ment overflow flag v. see the instruction set description for detailed information. bit 3 - v: two?s complement overflow flag the two?s complement overflow flag v supports two?s complement arithmetic. see the instruction set description for detailed information. bit 2 - n: negative flag the negative flag n indicates a negative result from an arithmetical or logical operation. see the instruction set description for detailed information. bit 1 - z: zero flag the zero flag z indicates a zero result from an arithmetical or logical operation. see the instruction set description for detailed information. bit 0 - c: carry flag the carry flag c indicates a carry in an arithmetical or logical operation. see the instruc- tion set description for detailed information. note that the status register is not automatically stored when entering an interrupt rou- tine and restored when returning from an interrupt routine. this must be handled by software. reset and interrupt handling the attiny11 provides four different interrupt sources and the attiny12 provides five. these interrupts and the separate reset vector each have a separate program vector in the program memory space. all the interrupts are assigned individual enable bits which must be set (one) together with the i-bit in the status register in order to enable the interrupt. the lowest addresses in the program memory space are automatically defined as the reset and interrupt vectors. the complete list of vectors is shown in table 5. the list also determines the priority levels of the different interrupts. the lower the address, the higher the priority level. reset has the highest priority, and next is int0 ? the external interrupt request 0, etc. 16 attiny11/12 1006d?avr?07/03 the most typical and general program setup for the reset and interrupt vector addresses for the attiny11 are: address labels code comments $000 rjmp reset ; reset handler $001 rjmp ext_int0 ; irq0 handler $002 rjmp pin_change ; pin change handler $003 rjmp tim0_ovf ; timer0 overflow handler $004 rjmp ana_comp ; analog comparator handler ; $005 main: 17 attiny11/12 1006d?avr?07/03 reset sources the attiny11/12 provides three or four sources of reset: power-on reset. the mcu is reset when the supply voltage is below the power-on reset threshold (v pot ). external reset. the mcu is reset when a low level is present on the reset pin for more than 50 ns. watchdog reset. the mcu is reset when the watchdog timer period expires and the watchdog is enabled. brown-out reset. the mcu is reset when the supply voltage v cc falls below a certain voltage (attiny12 only). during reset, all i/o registers are then set to their initial values, and the program starts execution from address $000. the instruction placed in address $000 must be an rjmp ? relative jump ? instruction to the reset handling routine. if the program never enables an interrupt source, the interrupt vectors are not used, and regular program code can be placed at these locations. the circuit diagram in figure 16 shows the reset logic for the attiny11. figure 17 shows the reset logic for the attiny12. table 6 defines the electrical parameters of the reset circuitry for attiny11. table 8 shows the parameters of the reset circuitry for attiny12. figure 16. reset logic for the attiny11 note: 1. the power-on reset will not work unless the supply voltage has been below v pot (falling). table 6. reset characteristics for the attiny11 symbol parameter min typ max units v pot (1) power-on reset threshold voltage (rising) 1.0 1.4 1.8 v power-on reset threshold voltage (falling) 0.4 0.6 0.8 v v rst reset pin threshold voltage 0.6 v cc v power-on reset circuit reset circuit watchdog timer on-chip rc oscillator 20-stage ripple counter q3 q19 q13 q9 q q s r internal reset por vcc reset counter reset fstrt cksel 18 attiny11/12 1006d?avr?07/03 power-on reset for the attiny11 a power-on reset (por) circuit ensures that the device is reset from power-on. as shown in figure 16, an internal timer is clocked from the watchdog timer. this timer pre- vents the mcu from starting a certain period after v cc has reached the power-on threshold voltage ? v pot . see figure 18. the total reset period is the delay time-out period ? t tout . the fstrt fuse bit in the flash can be programmed to give a shorter start-up time.the start-up times for the different clock options are shown in the following table. the watchdog oscillator is used for timing the start-up time, and this oscillator is voltage dependent as shown in the section ?attiny11 typical characteristics? on page 60. if the built-in start-up delay is sufficient, reset can be connected to v cc directly or via an external pull-up resistor. by holding the reset pin low for a period after v cc has been applied, the power-on reset period can be extended. refer to figure 19 for a tim- ing example on this. table 7. start-up times for the attiny11 (v cc = 2.7v) selected clock option start-up time t tout fstrt unprogrammed fstrt programmed external crystal 67 ms 4.2 ms external ceramic resonator 67 ms 4.2 ms external low-frequency crystal 4.2 s 4.2 s external rc oscillator 4.2 ms 67 s internal rc oscillator 4.2 ms 67 s external clock 4.2 ms 5 clocks from reset, 2 clocks from power-down 19 attiny11/12 1006d?avr?07/03 figure 17. reset logic for the attiny12 note: 1. the power-on reset will not work unless the supply voltage has been below v pot (falling). table 8. reset characteristics for the attiny12 symbol parameter condition min typ max units v pot (1) power-on reset threshold voltage (rising) bod disabled 1.0 1.4 1.8 v bod enabled 0.6 1.2 1.8 v power-on reset threshold voltage (falling) bod disabled 0.4 0.6 0.8 v bod enabled 0.6 1.2 1.8 v v rst reset pin threshold voltage 0.6v cc v v bot brown-out reset threshold voltage (bodlevel = 1) 1.5 1.8 1.9 v (bodlevel = 0) 2.3 2.7 2.8 mcu status register (mcusr) brown-out reset circuit boden bodlevel delay counters cksel[3:0] ck full wdrf borf extrf porf data bus power-on reset circuit on-chip rc oscillator 20 attiny11/12 1006d?avr?07/03 note: 1. due to the limited number of clock cycles in the start-up period, it is recommended that ceramic resonator be used. this table shows the start-up times from reset. from sleep, only the clock counting part of the start-up time is used. the watchdog oscillator is used for timing the real-time part of the start-up time. the number of wdt oscillator cycles used for each time-out is shown in table 10. the frequency of the watchdog oscillator is voltage dependent as shown in the section ?attiny11 typical characteristics? on page 60. note that the bodlevel fuse can be used to select start-up times even if the brown- out detection is disabled (by leaving the boden fuse unprogrammed). the device is shipped with cksel3..0 = 0010. table 9. attiny12 clock options and start-up times cksel3..0 clock source start-up time, v cc = 1.8v, bodlevel unprogrammed start-up time, v cc = 2.7v, bodlevel programmed 1111 ext. crystal/ceramic resonator (1) 1k ck 1k ck 1110 ext. crystal/ceramic resonator (1) 3.6 ms + 1k ck 4.2 ms + 1k ck 1101 ext. crystal/ceramic resonator (1) 57 ms 1k ck 67 ms + 1k ck 1100 ext. crystal/ceramic resonator 16k ck 16k ck 1011 ext. crystal/ceramic resonator 3.6 ms + 16k ck 4.2 ms + 16k ck 1010 ext. crystal/ceramic resonator 57 ms + 16k ck 67 ms + 16k ck 1001 ext. low-frequency crystal 57 ms + 1k ck 67 ms + 1k ck 1000 ext. low-frequency crystal 57 ms + 32k ck 67 ms + 32k ck 0111 ext. rc oscillator 6 ck 6 ck 0110 ext. rc oscillator 3.6 ms + 6 ck 4.2 ms + 6 ck 0101 ext. rc oscillator 57 ms + 6 ck 67 ms + 6 ck 0100 int. rc oscillator 6 ck 6 ck 0011 int. rc oscillator 3.6 ms + 6 ck 4.2 ms + 6 ck 0010 int. rc oscillator 57 ms + 6 ck 67 ms + 6 ck 0001 ext. clock 6 ck 6 ck 0000 ext. clock 3.6 ms + 6 ck 4.2 ms + 6 ck table 10. number of watchdog oscillator cycles bodlevel time-out number of cycles unprogrammed 3.6 ms (at v cc = 1.8v) 256 unprogrammed 57 ms (at v cc = 1.8v) 4k programmed 4.2 ms (at v cc = 2.7v) 1k programmed 67 ms (at v cc = 2.7v) 16k 21 attiny11/12 1006d?avr?07/03 power-on reset for the attiny12 a power-on reset (por) pulse is generated by an on-chip detection circuit. the detec- tion level is nominally 1.4v. the por is activated whenever v cc is below the detection level. the por circuit can be used to trigger the start-up reset, as well as detect a fail- ure in supply voltage. the power-on reset (por) circuit ensures that the device is reset from power-on. reaching the power-on reset threshold voltage invokes a delay counter, which deter- mines the delay for which the device is kept in reset after v cc rise. the time-out period of the delay counter can be defined by the user through the cksel fuses. the different selections for the delay period are presented in table 9. the reset signal is activated again, without any delay, when the v cc decreases below detection level. if the built-in start-up delay is sufficient, reset can be connected to v cc directly or via an external pull-up resistor. see figure 18. by holding the reset pin low for a period after v cc has been applied, the power-on reset period can be extended. refer to fig- ure 19 for a timing example on this. figure 18. mcu start-up, reset tied to v cc . figure 19. mcu start-up, reset extended externally external reset an external reset is generated by a low level on the reset pin. reset pulses longer than 50 ns will generate a reset, even if the clock is not running. shorter pulses are not guaranteed to generate a reset. when the applied signal reaches the reset threshold voltage ? v rst ? on its positive edge, the delay timer starts the mcu after the time-out period (t tout ) has expired. v cc reset time-out internal reset t tout v pot v rst v cc time-out internal reset reset t tout v pot v rst 22 attiny11/12 1006d?avr?07/03 figure 20. external reset during operation brown-out detection (attiny12) attiny12 has an on-chip brown-out detection (bod) circuit for monitoring the v cc level during the operation. the bod circuit can be enabled/disabled by the fuse boden. when boden is enabled (boden programmed), and v cc decreases below the trigger level, the brown-out reset is immediately activated. when v cc increases above the trig- ger level, the brown-out reset is deactivated after a delay. the delay is defined by the user in the same way as the delay of por signal, in table 5. the trigger level for the bod can be selected by the fuse bodlevel to be 1.8v (bodlevel unprogrammed), or 2.7v (bodlevel programmed). the trigger level has a hysteresis of 50 mv to ensure spike-free brown-out detection. the bod circuit will only detect a drop in v cc if the voltage stays below the trigger level for longer than 7 s for trigger level 2.7v, 24 s for trigger level 1.8v (typical values). figure 21. brown-out reset during operation (attiny12) note: the hysteresis on v bot : v bot + = v bot + 25 mv, v bot- = v bot - 25 mv. v cc time-out internal reset reset t tout v rst v cc reset time-out internal reset v bot- v bot+ t tout 23 attiny11/12 1006d?avr?07/03 watchdog reset when the watchdog times out, it will generate a short reset pulse of 1 ck cycle dura- tion. on the falling edge of this pulse, the delay timer starts counting the time-out period (t tout ). refer to page 36 for details on operation of the watchdog. figure 22. watchdog reset during operation mcu status register ? mcusr of the attiny11 the mcu status register provides information on which reset source caused an mcu reset. bit 7..2 - res: reserved bits these bits are reserved bits in the attiny11 and always read as zero. bit 1 - extrf: external reset flag after a power-on reset, this bit is undefined (x). it will be set by an external reset. a watchdog reset will leave this bit unchanged. bit 0 - porf: power-on reset flag this bit is set by a power-on reset. a watchdog reset or an external reset will leave this bit unchanged. to summarize, the following table shows the value of these two bits after the three modes of reset. to identify a reset condition, the user software should clear both the porf and extrf bits as early as possible in the program. checking the porf and extrf values is done ck v cc bit 76543210 $34 ------extrfporfmcusr read/writerrrrrrr/wr/w initial value000000see bit description table 11. porf and extrf values after reset reset source extrf porf power-on undefined 1 external reset 1 unchanged watchdog reset unchanged unchanged 24 attiny11/12 1006d?avr?07/03 before the bits are cleared. if the bit is cleared before an external or watchdog reset occurs, the source of reset can be found by using the following truth table: mcu status register ? mcusr for the attiny12 the mcu status register provides information on which reset source caused an mcu reset. bit 7..4 - res: reserved bits these bits are reserved bits in the attiny12 and always read as zero. bit 3 - wdrf: watchdog reset flag this bit is set if a watchdog reset occurs. the bit is reset by a power-on reset, or by writ- ing a logic zero to the flag. bit 2 - borf: brown-out reset flag this bit is set if a brown-out reset occurs. the bit is reset by a power-on reset, or by writ- ing a logic zero to the flag. bit 1 - extrf: external reset flag this bit is set if an external reset occurs. the bit is reset by a power-on reset, or by writ- ing a logic zero to the flag. bit 0 - porf: power-on reset flag this bit is set if a power-on reset occurs. the bit is reset by writing a logic zero to the flag. to use the reset flags to identify a reset condition, the user should read and then reset the mcusr as early as possible in the program. if the register is cleared before another reset occurs, the source of the reset can be found by examining the reset flags. attiny12 internal voltage reference attiny12 features an internal voltage reference with a nominal voltage of 1.22v. this reference is used for brown-out detection, and it can be used as an input to the analog comparator. voltage reference enable signals and start-up time the voltage reference has a start-up time that may influence the way it should be used. the maximum start-up time is 10s. to save power, the reference is not always turned on. the reference is on during the following situations: table 12. reset source identification extrf porf reset source 0 0 watchdog reset 1 0 external reset 0 1 power-on reset 1 1 power-on reset bit 76543210 $34 ----wdrfborfextrfporfmcusr read/write r r r r r/w r/w r/w r/w initial value 0 0 0 0 see bit description 25 attiny11/12 1006d?avr?07/03 1. when bod is enabled (by programming the boden fuse) 2. when the bandgap reference is connected to the analog comparator (by setting the ainbg bit in acsr) thus, when bod is not enabled, after setting the ainbg bit, the user must always allow the reference to start up before the output from the analog comparator is used. the bandgap reference uses approximately 10 a , and to reduce power consumption in power-down mode, the user can turn off the reference when entering this mode. interrupt handling the attiny11/12 has two 8-bit interrupt mask control registers; gimsk ? general inter- rupt mask register and timsk ? timer/counter interrupt mask register. when an interrupt occurs, the global interrupt enable i-bit is cleared (zero) and all inter- rupts are disabled. the user software can set (one) the i-bit to enable nested interrupts. the i-bit is set (one) when a return from interrupt instruction ? reti ? is executed. when the program counter is vectored to the actual interrupt vector in order to execute the interrupt handling routine, hardware clears the corresponding flag that generated the interrupt. some of the interrupt flags can also be cleared by writing a logic one to the flag bit position(s) to be cleared. if an interrupt condition occurs when the corresponding interrupt enable bit is cleared (zero), the interrupt flag will be set and remembered until the interrupt is enabled, or the flag is cleared by software. if one or more interrupt conditions occur when the global interrupt enable bit is cleared (zero), the corresponding interrupt flag(s) will be set and remembered until the global interrupt enable bit is set (one), and will be executed by order of priority. note that external level interrupt does not have a flag, and will only be remembered for as long as the interrupt condition is active. note that the status register is not automatically stored when entering an interrupt rou- tine and restored when returning from an interrupt routine. this must be handled by software. interrupt response time the interrupt execution response for all the enabled avr interrupts is 4 clock cycles minimum. after the 4 clock cycles, the program vector address for the actual interrupt handling routine is executed. during this 4-clock-cycle period, the program counter (9 bits) is pushed onto the stack. the vector is normally a relative jump to the interrupt rou- tine, and this jump takes 2 clock cycles. if an interrupt occurs during execution of a multi-cycle instruction, this instruction is completed before the interrupt is served. in attiny12, if an interrupt occurs when the mcu is in sleep mode, the interrupt response time is increased by 4 clock cycles. a return from an interrupt handling routine takes 4 clock cycles. during these 4 clock cycles, the program counter (9 bits) is popped back from the stack, and the i-flag in sreg is set. when avr exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served. general interrupt mask register ? gimsk bit 7 6 5 4 3 2 1 0 $3b - int0 pcie - - - - - gimsk read/write r r/w r/w r r r r r initial value 0 0 0 0 0 0 0 0 26 attiny11/12 1006d?avr?07/03 bit 7 - res: reserved bit this bit is a reserved bit in the attiny11/12 and always reads as zero. bit 6 - int0: external interrupt request 0 enable when the int0 bit is set (one) and the i-bit in the status register (sreg) is set (one), the external pin interrupt is enabled. the interrupt sense control0 bits 1/0 (isc01 and isc00) in the mcu general control register (mcucr) define whether the external interrupt is activated on rising or falling edge, on pin change, or low level of the int0 pin. activity on the pin will cause an interrupt request even if int0 is configured as an output. the corresponding interrupt of external in terrupt request 0 is executed from program memory address $001. see also ?external interrupts.? bit 5 - pcie: pin change interrupt enable when the pcie bit is set (one) and the i-bit in the status register (sreg) is set (one), the interrupt on pin change is enabled. any change on any input or i/o pin will cause an interrupt. the corresponding interrupt of pin change interrupt request is executed from program memory address $002. see also ?pin change interrupt.? bits 4..0 - res: reserved bits these bits are reserved bits in the attiny11/12 and always read as zero. general interrupt flag register ? gifr bit 7 - res: reserved bit this bit is a reserved bit in the attiny11/12 and always reads as zero. bit 6 - intf0: external interrupt flag0 when an edge on the int0 pin triggers an interrupt request, the corresponding interrupt flag, intf0 becomes set (one). if the i-bit in sreg and the corresponding interrupt enable bit, int0 bit in gimsk, are set (one), the mcu will jump to the interrupt vector. the flag is cleared when the interrupt routine is executed. alternatively, the flag can be cleared by writing a logical one to it. the flag is always cleared when int0 is configured as level interrupt. bit 5 - pcif: pin change interrupt flag when an event on any input or i/o pin triggers an interrupt request, pcif becomes set (one). if the i-bit in sreg and the pcie bit in gimsk are set (one), the mcu will jump to the interrupt vector at address $002. the flag is cleared when the interrupt routine is executed. alternatively, the flag can be cleared by writing a logical one to it. bits 4..0 - res: reserved bits these bits are reserved bits in the attiny11/12 and always read as zero. timer/counter interrupt mask register ? timsk bit 7 6 5 4 3 2 1 0 $3a - intf0 pcif - - - - - gifr read/write r r/w r/w r r r r r initial value 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 27 attiny11/12 1006d?avr?07/03 bit 7..2 - res: reserved bits these bits are reserved bits in the attiny11/12 and always read as zero. bit 1 - toie0: timer/counter0 overflow interrupt enable when the toie0 bit is set (one) and the i-bit in the status register is set (one), the timer/counter0 overflow interrupt is enabled. the corresponding interrupt (at vector $003) is executed if an overflow in timer/counter0 occurs, i.e., when the overflow flag (timer0) is set (one) in the timer/counter interrupt flag register ? tifr. bit 0 - res: reserved bit this bit is a reserved bit in the attiny11/12 and always reads as zero. timer/counter interrupt flag register ? tifr bits 7..2 - res: reserved bits these bits are reserved bits in the attiny11/12 and always read as zero. bit 1 - tov0: timer/counter0 overflow flag the bit tov0 is set (one) when an overflow occurs in timer/counter0. tov0 is cleared by hardware when executing the corresponding interrupt handling vector. alternatively, tov0 is cleared by writing a logical one to the flag. when the sreg i-bit, toie0 (timer/counter0 overflow interrupt enable), and tov0 are set (one), the timer/counter0 overflow interrupt is executed. bit 0 - res: reserved bit this bit is a reserved bit in the attiny11/12 and always reads as zero. external interrupt the external interrupt is triggered by the int0 pin. observe that, if enabled, the interrupt will trigger even if the int0 pin is configured as an output. this feature provides a way of generating a software interrupt. the external interrupt can be triggered by a falling or ris- ing edge, a pin change, or a low level. this is set up as indicated in the specification for the mcu control register ? mcucr. when the external interrupt is enabled and is con- figured as level triggered, the interrupt will trigger as long as the pin is held low. the external interrupt is set up as described in the specification for the mcu control register ? mcucr. pin change interrupt the pin change interrupt is triggered by any change on any input or i/o pin. change on pins pb2..0 will always cause an interrupt. change on pins pb5..3 will cause an inter- rupt if the pin is configured as input or i/o, as described in the section ?pin descriptions? on page 5. observe that, if enabled, the interrupt will trigger even if the changing pin is configured as an output. this feature provides a way of generating a software interrupt. also observe that the pin change interrupt will trigger even if the pin activity triggers $39 - - - - - - toie0 - timsk read/write r r r r r r r/w r initial value 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 $38 -- ----tov0-tifr read/write r r r r r r r/w r initial value 0 0 0 0 0 0 0 0 28 attiny11/12 1006d?avr?07/03 another interrupt, for example, the external interrupt. this implies that one external event might cause several interrupts. the values on the pins are sampled before detecting edges. if pin change interrupt is enabled, pulses that last longer than one cpu clock period will generate an interrupt. shorter pulses are not guaranteed to generate an interrupt. 29 attiny11/12 1006d?avr?07/03 mcu control register ? mcucr the mcu control register contains control bits for general mcu functions. note: the pull-up disable (pud) bit is only available in attiny12. bit 7 - res: reserved bit this bit is a reserved bit in the attiny11/12 and always reads as zero. bit 6 - res: reserved bit in attiny11 this bit is a reserved bit in the attiny11 and always reads as zero. bit 6 - pud: pull-up disable in attiny12 setting this bit, disables all pull-ups on port b. if this bit is cleared, the pull-ups can be individually enabled as described in section ?i/o port b? on page 43. bit 5 - se: sleep enable the se bit must be set (one) to make the mcu enter the sleep mode when the sleep instruction is executed. to avoid the mcu entering the sleep mode unless it is the pro- grammer?s purpose, it is recommended to set the sleep enable se bit just before the execution of the sleep instruction. bit 4 - sm: sleep mode this bit selects between the two available sleep modes. when sm is cleared (zero), idle mode is selected as sleep mode. when sm is set (one), power-down mode is selected as sleep mode. for details, refer to the paragraph ?sleep modes? below. bits 3, 2 - res: reserved bits these bits are reserved bits in the attiny11/12 and always read as zero. bits 1, 0 - isc01, isc00: interrupt sense control0 bit 1 and bit 0 the external interrupt 0 is activated by the external pin int0 if the sreg i-flag and the corresponding interrupt mask are set. the following table shows how to set the isc bits to generate an external interrupt: the value on the int0 pin is sampled before detecting edges. if edge interrupt is selected, pulses that last longer than one cpu clock period will generate an interrupt. shorter pulses are not guaranteed to generate an interrupt. if low-level interrupt is selected, the low level must be held until the completion of the currently executing bit 76543210 $35 - (pud) se sm - - isc01 isc00 mcucr read/write r r(/w) r/w r/w r r r/w r/w initial value00000000 table 13. interrupt 0 sense control isc01 isc00 description 0 0 the low level of int0 generates an interrupt request. 0 1 any change on int0 generates an interrupt request 1 0 the falling edge of int0 generates an interrupt request. 1 1 the rising edge of int0 generates an interrupt request. 30 attiny11/12 1006d?avr?07/03 instruction to generate an interrupt. if enabled, a level-triggered interrupt will generate an interrupt request as long as the pin is held low. 31 attiny11/12 1006d?avr?07/03 sleep modes for the attiny11 to enter the sleep modes, the se bit in mcucr must be set (one) and a sleep instruc- tion must be executed. the sm bit in the mcucr register selects which sleep mode (idle or power-down) will be activated by the sleep instruction. if an enabled interrupt occurs while the mcu is in a sleep mode, the mcu awakes, executes the interrupt rou- tine, and resumes execution from the instruction following sleep. on wake-up from power down mode on pin change, two instruction cycles are executed before the pin change interrupt flag is updated. during these cycles, the prosessor executes intruc- tions, but the interrupt condition is not readable, and the interrupt routine has not startet yet. the contents of the register file and i/o memory are unaltered. if a reset occurs dur- ing sleep mode, the mcu wakes up and executes from the reset vector. idle mode when the sm bit is cleared (zero), the sleep instruction forces the mcu into the idle mode, stopping the cpu but allowing timer/counters, watchdog and the interrupt sys- tem to continue operating. this enables the mcu to wake up from external triggered interrupts as well as internal ones like timer overflow interrupt and watchdog reset. if wake-up from the analog comparator interrupt is not required, the analog comparator can be powered down by setting the acd-bit in the analog comparator control and sta- tus register ? acsr. this will reduce power consumption in idle mode. when the mcu wakes up from idle mode, the cpu starts program execution immediately. power-down mode when the sm bit is set (one), the sleep instruction forces the mcu into the power- down mode. in this mode, the external oscillator is stopped, while the external interrupts and the watchdog (if enabled) continue operating. only an external reset, a watchdog reset (if enabled), an external level interrupt, or an pin change interrupt can wake up the mcu. note that if a level-triggered or pin change interrupt is used for wake-up from power- down, the changed level must be held for a time longer than the reset delay period of t tout . otherwise, the mcu will fail to wake up. sleep modes for the attiny12 to enter the sleep modes, the se bit in mcucr must be set (one) and a sleep instruc- tion must be executed. the sm bit in the mcucr register selects which sleep mode (idle or power-down) will be activated by the sleep instruction. if an enabled interrupt occurs while the mcu is in a sleep mode, the mcu awakes. the cpu is then halted for four cycles, it executes the interrupt routine, and resumes execution from the instruction following sleep. the contents of the register file and i/o memory are unaltered. if a reset occurs during sleep mode, the mcu wakes up and executes from the reset vector. idle mode when the sm bit is cleared (zero), the sleep instruction forces the mcu into the idle mode stopping the cpu but allowing time r/counters, watchdog and the interrupt sys- tem to continue operating. this enables the mcu to wake up from external triggered interrupts as well as internal ones like timer overflow interrupt and watchdog reset. if wake-up from the analog comparator interrupt is not required, the analog comparator can be powered down by setting the acd-bit in the analog comparator control and sta- tus register ? acsr. this will reduce power consumption in idle mode. power-down mode when the sm bit is set (one), the sleep instruction forces the mcu into the power- down mode. in this mode, the external oscillator is stopped, while the external interrupts and the watchdog (if enabled) continue operating. only an external reset, a watchdog reset (if enabled), an external level interrupt, or a pin change interrupt can wake up the mcu. 32 attiny11/12 1006d?avr?07/03 note that if a level triggered or pin change interrupt is used for wake-up from power- down mode, the changed level must be held for a time to wake up the mcu. this makes the mcu less sensitive to noise. the wake-up period is equal to the clock-counting part of the reset period (see table 9). the mcu will wake up from the power-down if the input has the required level for two watchdog oscillator cycles. if the wake-up period is shorter than two watchdog oscillator cycles, the mcu will wake up if the input has the required level for the duration of the wake-up period. if the wake-up condition disap- pears before the wake-up period has expired, the mcu will wake up from power-down without executing the corresponding interrupt. the period of the watchdog oscillator is 2.7 s (nominal) at 3.0v and 25 c. the frequency of the watchdog oscillator is voltage dependent as shown in the section ?attiny11 typical characteristics? on page 60. when waking up from power-down mode, there is a delay from the wake-up condition occurs until the wake-up becomes effective. this allows the clock to restart and become stable after having been stopped. the wake-up period is defined by the same cksel fuses that define the reset time-out period. attiny12 calibrated internal rc oscillator in attiny12, the calibrated internal oscillator provides a fixed 1.2 mhz (nominal) clock at 5v and 25 c. this clock may be used as the system clock. see the section ?clock options? on page 5 for information on how to select this clock as the system clock. this oscillator can be calibrated by writing the calibration byte to the osccal register. when this oscillator is used as the chip clock, the watchdog oscillator will still be used for the watchdog timer and for the reset time-out. for details on how to use the pre-pro- grammed calibration value, see the section ?calibration byte in attiny12? on page 47. at 5v and 25 o c, the pre-programmed calibration byte gives a frequency within 1% of the nominal frequency. oscillator calibration register ? osccal bits 7..0 - cal7..0: oscillator calibration value writing the calibration byte to this address will trim the internal oscillator to remove pro- cess variations from the oscillator frequency. when osccal is zero, the lowest available frequency is chosen. writing non-zero values to this register will increase the frequency of the internal oscillator. writing $ff to the register gives the highest available frequency. the calibrated oscillator is used to time eeprom access. if eeprom is written, do not calibrate to more than 10% above the nominal frequency. otherwise, the eeprom write may fail. table 14 shows the range for osccal. note that the oscillator is intended for calibration to 1.2 mhz, thus tuning to other values is not guaranteed. bit 76543210 $31 cal7 cal6 cal5 cal4 cal3 cal2 cal1 cal0 osccal read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 table 14. internal rc oscillator frequency range osccal value min frequency max frequency $00 0.6 mhz 1.2 mhz $7f 0.8 mhz 1.7 mhz $ff 1.2 mhz 2.5 mhz 33 attiny11/12 1006d?avr?07/03 timer/counter0 the attiny11/12 provides one general-purpos e 8-bit timer/counter ? timer/counter0. the timer/counter0 has prescaling selection from the 10-bit prescaling timer. the timer/counter0 can either be used as a timer with an internal clock timebase or as a counter with an external pin connection that triggers the counting. timer/counter prescaler figure 23 shows the timer/counter prescaler. figure 23. timer/counter0 prescaler the four different prescaled selections are: ck/8, ck/64, ck/256 and ck/1024 where ck is the oscillator clock. ck, external source and stop, can also be selected as clock sources. figure 24 shows the block diagram for timer/counter0. the 8-bit timer/counter0 can select clock so urce from ck, prescaled ck, or an external pin. in addition, it can be stopped as described in the specification for the timer/counter0 control register ? tccr0. the overflow status flag is found in the timer/counter interrupt flag register ? tifr. control signals are found in the timer/counter0 control register ? tccr0. the interrupt enable/disable settings for timer/counter0 are found in the timer/counter interrupt mask register ? timsk. when timer/counter0 is externally clocked, the external signal is synchronized with the oscillator frequency of the cpu. to ensure proper sampling of the external clock, the minimum time between two external clock transitions must be at least one internal cpu clock period. the external clock signal is sampled on the rising edge of the internal cpu clock. the 8-bit timer/counter0 features both a high-resolution and a high-accuracy usage with the lower prescaling opportunities. similarly, the high-prescaling opportunities make the timer/counter0 useful for lower-speed functions or exact-timing functions with infrequent actions. 10-bit t/c prescaler 0 timer/counter0 clock source tck0 ck t0 cs00 cs01 cs02 ck/8 ck/256 ck/1024 ck/64 34 attiny11/12 1006d?avr?07/03 figure 24. timer/counter0 block diagram timer/counter0 control register ? tccr0 bits 7..3 - res: reserved bits these bits are reserved bits in the attiny11/12 and always read as zero. bits 2,1,0 - cs02, cs01, cs00: clock select0, bit 2,1 and 0 the clock select0 bits 2,1 and 0 define the prescaling source of timer0. t0 bit 7 6 5 4 3 210 $33 - - - - - cs02 cs01 cs00 tccr0 read/write r r r r r r/w r/w r/w initial value 0 0 0 0 0 0 0 0 table 15. clock 0 prescale select cs02 cs01 cs00 description 0 0 0 stop, the timer/counter0 is stopped. 001ck 010ck/8 011ck/64 100ck/256 101ck/1024 1 1 0 external pin t0, falling edge 1 1 1 external pin t0, rising edge 35 attiny11/12 1006d?avr?07/03 the stop condition provides a timer enable/disable function. the ck down-divided modes are scaled directly from the ck oscillator clock. if the external pin modes are used for timer/counter0, transitions on pb2/(t0) will clock the counter even if the pin is configured as an output. this feature can give the user sw control of the counting. timer counter 0 ? tcnt0 the timer/counter0 is implemented as an up-counter with read and write access. if the timer/counter0 is written and a clock source is present, the timer/counter0 continues counting in the timer clock cycle following the write operation. bit 76543210 $32 msb lsb tcnt0 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 36 attiny11/12 1006d?avr?07/03 watchdog timer the watchdog timer is clocked from a separate on-chip oscillator. by controlling the watchdog timer prescaler, the watchdog reset interval can be adjusted as shown in table 16. see characterization data for typical values at other v cc levels. the wdr ? watchdog reset ? instruction resets the watchdog timer. eight different clock cycle periods can be selected to determine the reset period. if the reset period expires without another watchdog reset, the attiny11/12 resets and executes from the reset vector. for timing details on the watchdog reset, refer to page 23. to prevent unintentional disabling of the watchdog, a special turn-off sequence must be followed when the watchdog is disabled. refer to the description of the watchdog timer control register for details. figure 25. watchdog timer watchdog timer control register ? wdtcr bits 7..5 - res: reserved bits these bits are reserved bits in the attiny11/12 and w ill always read as zero. bit 4 - wdtoe: watchdog turn-off enable this bit must be set (one) when the wde bit is cleared. otherwise, the watchdog will not be disabled. once set, hardware will clear this bit to zero after four clock cycles. refer to the description of the wde bit for a watchdog disable procedure. bit 3 - wde: watchdog enable when the wde is set (one) the watchdog timer is enabled, and if the wde is cleared (zero) the watchdog timer function is disabled. wde can be cleared only when the wdtoe bit is set(one). to disable an enabled watchdog timer, the following procedure must be followed: 1 mhz at v cc = 5v 350 khz at v cc = 3v 110 khz at v cc = 2v oscillator bit 76543210 $21 - - - wdtoe wde wdp2 wdp1 wdp0 wdtcr read/write r r r r/w r/w r/w r/w r/w initial value00000000 37 attiny11/12 1006d?avr?07/03 1. in the same operation, write a logical one to wdtoe and wde. a logical one must be written to wde even though it is set to one before the disable operation starts. 2. within the next four clock cycles, write a logical 0 to wde. this disables the watchdog. bits 2..0 - wdp2, wdp1, wdp0: watchdog timer prescaler 2, 1 and 0 the wdp2, wdp1 and wdp0 bits determine the watchdog timer prescaling when the watchdog timer is enabled. the different prescaling values and their corresponding time-out periods are shown in table 16. note: the frequency of the watchdog oscillator is voltage dependent as shown in the section ?attiny11 typical characteristics? on page 60. the wdr ? watchdog reset ? instruction should always be executed before the watch- dog timer is enabled. this ensures that the reset period will be in accordance with the watchdog timer prescale settings. if the watchdog timer is enabled without reset, the watchdog timer may not start counting from zero. to avoid unintentional mcu resets, the watchdog timer should be disabled or reset before changing the watchdog timer prescale select. table 16. watchdog timer prescale select wdp2 wdp1 wdp0 number of wdt oscillator cycles typical time-out at v cc = 2.0v typical time-out at v cc = 3.0v typical time-out at v cc = 5.0v 0 0 0 16k cycles 0.15s 47 ms 15 ms 0 0 1 32k cycles 0.30s 94 ms 30 ms 0 1 0 64k cycles 0.60s 0.19 s 60 ms 0 1 1 128k cycles 1.2s 0.38 s 0.12 s 1 0 0 256k cycles 2.4s 0.75 s 0.24 s 1 0 1 512k cycles 4.8s 1.5 s 0.49 s 1 1 0 1,024k cycles 9.6s 3.0 s 0.97 s 1 1 1 2,048k cycles 19s 6.0 s 1.9 s 38 attiny11/12 1006d?avr?07/03 attiny12 eeprom read/write access the eeprom access registers are accessible in the i/o space. the write access time is in the range of 3.1 - 6.8 ms, depending on the frequency of the calibrated rc oscillator. see table 17 for details. a self-timing function lets the user software detect when the next byte can be written. a special eeprom ready interrupt can be set to trigger when the eeprom is ready to accept new data. the minimum volt- age for writing to the eeprom is 2.2v. in order to prevent unintentional eeprom writes, a two-state write procedure must be followed. refer to the description of the eeprom control register for details on this. when the eeprom is written, the cpu is halted for two clock cycles before the next instruction is executed. when the eeprom is read, the cpu is halted for four clock cycles before the next instruction is executed. eeprom address register ? eear the eeprom address register ? eear specifies the eeprom address in the 64-byte eeprom space. the eeprom data bytes are addressed linearly between 0 and 63. during reset, the eear register is not cleared. instead, the data in the register is kept. eeprom data register ? eedr bits 7..0 - eedr7.0: eeprom data for the eeprom write operation, the eedr register contains the data to be written to the eeprom in the address given by the eear register. for the eeprom read opera- tion, the eedr contains the data read out from the eeprom at the address given by eear. eeprom control register ? eecr bit 7..4 - res: reserved bits these bits are reserved bits in the attiny12 and will always read as zero. bit 3 - eerie: eeprom ready interrupt enable when the i-bit in sreg and eerie are set (one), the eeprom ready interrupt is enabled. when cleared (zero), the interrupt is disabled. the eeprom ready interrupt generates a constant interrupt when eewe is cleared (zero). bit 76543210 $1e - - eear5 eear4 eear3 eear2 eear1 eear0 eear read/write r r r/w r/w r/w r/w r/w r/w initial value 0 0 x x x x x x bit 76543210 $1d msb lsb eedr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543 2 10 $1c - - - - eerie eemwe eewe eere eecr read/write r r r r r/w r/w r/w r/w initial value 0 0 0 0 0 0 x 0 39 attiny11/12 1006d?avr?07/03 bit 2 - eemwe: eeprom master write enable the eemwe bit determines whether setting eewe to one causes the eeprom to be written. when eemwe is set (one), setting eewe will write data to the eeprom at the selected address. if eemwe is zero, setting eewe will have no effect. when eemwe has been set (one) by software, hardware clears the bit to zero after four clock cycles. see the description of the eewe bit for a eeprom write procedure. bit 1 - eewe: eeprom write enable the eeprom write enable signal eewe is the write strobe to the eeprom. when address and data are correctly set up, the eewe bit must be set to write the value into the eeprom. the eemwe bit must be set when the logical one is written to eewe, otherwise no eeprom write takes place. the following procedure should be followed when writing the eeprom (the order of steps 2 and 3 is unessential): 1. wait until eewe becomes zero. 2. write new eeprom address to eear (optional). 3. write new eeprom data to eedr (optional). 4. write a logical one to the eemwe bit in eecr (to be able to write a logical one to the eemwe bit, the eewe bit must be written to zero in the same cycle). 5. within four clock cycles after setting eemwe, write a logical one to eewe. caution: an interrupt between step 4 and step 5 will make the write cycle fail, since the eeprom master write enable will time-out. if an interrupt routine accessing the eeprom is interrupting another eeprom access, the eear or eedr register will be modified, causing the interrupted eeprom access to fail. it is recommended to have the global interrupt flag cleared during the four last steps to avoid these problems. when the write access time has elapsed, the eewe bit is cleared (zero) by hardware. the user software can poll this bit and wait for a zero before writing the next byte. when eewe has been set, the cpu is halted for two cycles before the next instruction is executed. bit 0 - eere: eeprom read enable the eeprom read enable signal eere is the read strobe to the eeprom. when the correct address is set up in the eear register, the eere bit must be set. when the eere bit is cleared (zero) by hardware, requested data is found in the eedr register. the eeprom read access takes one instruction and there is no need to poll the eere bit. when eere has been set, the cpu is halted for four cycles before the next instruc- tion is executed. the user should poll the eewe bit before starting the read operation. if a write operation is in progress when new data or address is written to the eeprom i/o registers, the write operation w ill be interrupted, and the result is undefined. the calibrated oscillator is used to time eeprom. in table 17 the typical programming time is listed for eeprom access from the cpu. table 17. typical eeprom programming times parameter number of calibrated rc oscillator cycles min programming time max programming time eeprom write (from cpu) 4096 3.1 ms 6.8 ms 40 attiny11/12 1006d?avr?07/03 prevent eeprom corruption during periods of low v cc , the eeprom data can be corrupted because the supply volt- age is too low for the cpu and the eeprom to operate properly. these issues are the same as for board-level systems using the eeprom, and the same design solutions should be applied. an eeprom data corruption can be caused by two situations when the voltage is too low. first, a regular write sequence to the eeprom requires a minimum voltage to operate correctly. secondly, the cpu itself can execute instructions incorrectly if the supply voltage for executing instructions is too low. eeprom data corruption can easily be avoided by following these design recommen- dations (one is sufficient): 1. keep the avr reset active (low) during periods of insufficient power supply voltage. this can be done by enabling the internal brown-out detector (bod) if the operating speed matches the detection level. if not, an external low v cc reset protection circuit can be applied. 2. keep the avr core in power-down sleep mode during periods of low v cc . this will prevent the cpu from attempting to decode and execute instructions, effec- tively protecting the eeprom registers from unintentional writes. 3. store constants in flash memory if the ability to change memory contents from software is not required. flash memory can not be updated by the cpu, and will not be subject to corruption. 41 attiny11/12 1006d?avr?07/03 analog comparator the analog comparator compares the input values on the positive input pb0 (ain0) and negative input pb1 (ain1). when the voltage on the positive input pb0 (ain0) is higher than the voltage on the negative input pb1 (ain1), the analog comparator output (aco) is set (one). the comparator?s output can trigger a separate interrupt, exclusive to the analog comparator. the user can select interrupt triggering on comparator output rise, fall or toggle. a block diagram of the comparator and its surrounding logic is shown in figure 26. figure 26. analog comparator block diagram. analog comparator control and status register ? acsr note: ainbg is only available in attiny12. bit 7 - acd: analog comparator disable when this bit is set (one), the power to the analog comparator is switched off. this bit can be set at any time to turn off the analog comparator. when changing the acd bit, the analog comparator interrupt must be disabled by clearing the acie bit in acsr. otherwise an interrupt can occur when the bit is changed. bit 6 - ainbg: analog comparator bandgap select in attiny12 in attiny12, when this bit is set, a fixed bandgap voltage of 1.22 0.05v replaces the normal input to the positive input (ain0) of the comparator. when this bit is cleared, the normal input pin pb0 is applied to the positive input of the comparator. bit 6- res: reserved bit in attiny11 this bit is a reserved bit in the attiny11 and will always read as zero. bit 5 - aco: analog comparator output aco is directly connected to the comparator output. bit 4 - aci: analog comparator interrupt flag this bit is set (one) when a comparator output event triggers the interrupt mode defined by aci1 and aci0. the analog comparator interrupt routine is executed if the acie bit is set (one) and the i-bit in sreg is set (one). aci is cleared by hardware when execut- internal voltage reference (attiny12 only) mux ainbg bit 7 6 543210 $08 acd (ainbg) aco aci acie - acis1 acis0 acsr read/write r/w r(/w) r r/w r/w r r/w r/w initial value 0 0 x 0 0 0 0 0 42 attiny11/12 1006d?avr?07/03 ing the corresponding interrupt handling vector. alternatively, aci is cleared by writing a logic one to the flag. bit 3 - acie: analog comparator interrupt enable when the acie bit is set (one) and the i-bit in the status register is set (one), the ana- log comparator interrupt is activated. when cleared (zero), the interrupt is disabled. bit 2 - res: reserved bit this bit is a reserved bit in the attiny11/12 and will always read as zero. bits 1,0 - acis1, acis0: analog comparator interrupt mode select these bits determine which comparator events that trigger the analog comparator inter- rupt. the different settings are shown in table 18. note: when changing the acis1/acis0 bits, the analog comparator interrupt must be dis- abled by clearing its interrupt enable bit in the acsr register. otherwise, an interrupt can occur when the bits are changed. caution: using the sbi or cbi instruction on bits other than aci in this register will write a one back into aci if it is read as set, thus clearing the flag. table 18. acis1/acis0 settings acis1 acis0 interrupt mode 0 0 comparator interrupt on output toggle 01reserved 1 0 comparator interrupt on falling output edge 1 1 comparator interrupt on rising output edge 43 attiny11/12 1006d?avr?07/03 i/o port b all avr ports have true read-modify-write functionality when used as general digital i/o ports. this means that the direction of one port pin can be changed without unintention- ally changing the direction of any other pin with the sbi and cbi instructions. the same applies for changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input). port b is a 6-bit bi-directional i/o port. three i/o memory address locations are allocated for port b, one each for the data register ? portb, $18, data direction register ? ddrb, $17, and the port b input pins ? pinb, $16. the port b input pins address is read only, while the data register and the data direction register are read/write. ports pb5..3 have special functions as described in the section ?pin descriptions? on page 5. if pb5 is not configured as external reset, it is input with no pull-up. on attiny12, it can also output a logical zero, acting as an open-drain output. note that, since pb5 only has one possible output value, the output functionality of this pin is con- trolled by the ddrb register alone. if pb4 and/or pb3 are not used for clock function, they are i/o pins. all i/o pins have individually selectable pull-ups. the port b output buffers on pb0 to pb4 can sink 20 ma and thus drive led displays directly. on attiny12, pb5 can sink 12 ma. when pins pb0 to pb4 are used as inputs and are externally pulled low, they will source current (i il ) if the internal pull-ups are activated. the port b pins with alternate functions are shown in table 19: when the pins pb2..0 are used for the alternate function, the ddrb and portb regis- ter has to be set according to the alternate function description. when pb5..3 are used for alternate functions, the values in the corresponding ddrb and portb bits are ignored. table 19. port b pins alternate functions port pin alternate functions device pb0 ain0 (analog comparator positive input) attiny11/12 mosi (data input line for memory downloading) attiny12 pb1 int0 (external interrupt0 input) attiny11/12 ain1 (analog comparator negative input) attiny11/12 mosi (data output line for memory downloading) attiny12 pb2 t0 (timer/counter0 external counter input) attiny11/12 sck (serial clock input for serial programming) attiny12 pb3 xtal1 (oscillator input) attiny11/12 pb4 xtal2 (oscillator output) attiny11/12 pb5 reset (external reset pin) attiny11/12 44 attiny11/12 1006d?avr?07/03 port b data register ? portb port b data direction register ? ddrb note: ddb5 is only available in attiny12. port b input pins address ? pinb the port b input pins address ? pinb ? is not a register, and this address enables access to the physical value on each port b pin. when reading portb, the port b data latch is read, and when reading pinb, the logical values present on the pins are read. port b as general digital i/o the lowermost five pins in port b have equal functionality when used as digital i/o pins. pbn, general i/o pin: the ddbn bit in the ddrb register selects the direction of this pin, if ddbn is set (one), pbn is configured as an output pin. if ddbn is cleared (zero), pbn is configured as an input pin. if portbn is set (one) when the pin is configured as an input pin, the mos pull-up resistor is activated. on attiny12 this feature can be dis- abled by setting the pull-up disable (pud) bit in the mcucr register. to switch the pull- up resistor off, the portbn can be cleared (zero), the pin can be configured as an out- put pin, or in attiny12, the pud bit can be set. the port pins are tri-stated when a reset condition becomes active, even if the clock is not running. n: 4,3?0, pin number. note that in attiny11, pb5 is input only. on attiny12, pb5 is input or open-drain output. because this pin is used for 12v programmi ng, there is no esd protection diode limiting the voltage on the pin to v cc + 0.5v. thus, special care should be taken to ensure that the voltage on this pin does not rise above v cc + 1v during normal operation. this may cause the mcu to reset or enter programming mode unintentionally. bit 76543210 $18 - - - portb4 portb3 portb2 portb1 portb0 portb read/write r r r r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 $17 - - (ddb5) ddb4 ddb3 ddb2 ddb1 ddb0 ddrb read/write r r r(/w) r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 $16 - - pinb5 pinb4 pinb3 pinb2 pinb1 pinb0 pinb read/writerrrrrrrr initial value 0 0 n/a n/a n/a n/a n/a n/a table 20. ddbn effects on port b pins ddbn portbn i/o pull-up comment 0 0 input no tri-state (hi-z) 0 1 input yes pbn will source current if ext. pulled low. in attiny12 pull-ups can be disabled by setting the pud bit. 1 0 output no push-pull zero output 1 1 output no push-pull one output 45 attiny11/12 1006d?avr?07/03 alternate functions of port b all port b pins are connected to a pin change detector that can trigger the pin change interrupt. see ?pin change interrupt? on page 27 for details. in addition, port b has the following alternate functions: reset - port b, bit 5 when the rstdisbl fuse is unprogrammed, this pin serves as external reset. when the rstdisbl fuse is programmed, this pin is a general input pin. in attiny12, it is also an open-drain output pin. xtal2 - port b, bit 4 xtal2, oscillator output. when this pin is not used for clock purposes, it is a general i/o pin. refer to section ?pin descriptions? on page 5 for details. xtal1 - port b, bit 3 xtal1, oscillator or clock input. when this pin is not used for clock purposes, it is a gen- eral i/o pin. refer to section ?pin descriptions? on page 5 for details. t0/sck - port b, bit 2 this pin can serve as the external counter clock input. see the timer/counter description for further details. if external timer/counter clocking is selected, activity on this pin will clock the counter even if it is configured as an output. in attiny12 and serial program- ming mode, this pin serves as the serial clock input, sck. int0/ain1/miso - port b, bit 1 this pin can serve as the external interrupt0 input. see the interrupt description for details on how to enable this interrupt. note that activity on this pin will trigger the inter- rupt even if the pin is configured as an output. this pin also serves as the negative input of the on-chip analog comparator. in attiny 12 and serial programming mode, this pin serves as the serial data input, miso. ain0/mosi - port b, bit 0 this pin also serves as the positive input of the on-chip analog comparator. in attiny12 and serial programming mode, this pin serves as the serial data output, mosi. during power-down mode, the schmitt triggers of the digital inputs are disconnected on the analog comparator input pins. this allows an analog voltage close to v cc /2 to be present during power-down without causing excessive power consumption. 46 attiny11/12 1006d?avr?07/03 memory programming program (and data) memory lock bits the attiny11/12 mcu provides two lock bits which can be left unprogrammed (?1?) or can be programmed (?0?) to obtain the additional features listed in table 21 . the lock bits can only be erased with the chip erase command . note: 1. in the high-voltage serial programming mode, further programming of the fuse bits are also disabled. program the fuse bits before programming the lock bits. fuse bits in attiny11 the attiny11 has five fuse bits, fstrt, rstdisbl and cksel2..0. fstrt: see table 7, ?start-up times for the attiny11 (v cc = 2.7v),? on page 18 for which value to use. default value is unprogrammed (?1?). when rstdisbl is programmed (?0?), the external reset function of pin pb5 is disabled. (1) default value is unprogrammed (?1?). cksel2..0: see table 3, ?device clocking options select,? on page 5, for which combination of cksel2..0 to use. default value is ?100?, internal rc oscillator. the status of the fuse bits is not affected by chip erase. note: 1. if the rstdisbl fuse is programmed, then the programming hardware should apply +12v to pb5 while the attiny11 is in power-on reset. if not, the part can fail to enter programming mode caused by drive contention on pb0. fuse bits in attiny12 the attiny12 has eight fuse bits, bodlevel, boden, spien, rstdisbl and cksel3..0. all the fuse bits are programmable in both high-voltage and low-voltage serial programming modes. changing the fuses does not have any effect while in pro- gramming mode. the bodlevel fuse selects the brown-out detection level and changes the start- up times. see ?brown-out detection (attiny12)? on page 22. see table 9, ?attiny12 clock options and start-up times,? on page 20. default value is programmed (?0?). when the boden fuse is programmed (?0?), the brown-out detector is enabled. see ?brown-out detection (attiny12)? on page 22. default value is unprogrammed (?1?). when the spien fuse bit is programmed (?0?), low-voltage serial program and data downloading is enabled. default value is programmed (?0?). unprogramming this fuse while in the low-voltage serial programming mode will disable future in- system downloading attempts. when the rstdisbl fuse is programmed (?0?), the external reset function of pin pb5 is disabled. (1) default value is unprogrammed (?1?). programming this fuse while in the low-voltage serial programming mode will disable future in-system downloading attempts. table 21. lock bit protection modes memory lock bits protection type mode lb1 lb2 1 1 1 no memory lock features enabled. 201 further programming of the flash (and eeprom for attiny12) is disabled. (1) 3 0 0 same as mode 2, and verify is also disabled. 47 attiny11/12 1006d?avr?07/03 cksel3..0 fuses: see table 3, ?device clocking options select,? on page 5 and table 9, ?attiny12 clock options and start-up times,? on page 20, for which combination of cksel3..0 to use. default value is ?0010?, internal rc oscillator with long start-up time. the status of the fuse bits is not affected by chip erase. note: 1. if the rstdisbl fuse is programmed, then the programming hardware should apply +12v to pb5 while the attiny12 is in power-on reset. if not, the part can fail to enter programming mode caused by drive contention on pb0 and/or pb5. signature bytes all atmel microcontrollers have a three-byte signature code which identifies the device. the three bytes reside in a separate address space. for the attiny11 they are: 1. $000: $1e (indicates manufactured by atmel) 2. $001: $90 (indicates 1 kb flash memory) 3. $002: $04 (indicates attiny11 device when signature byte $001 is $90) for the attiny12 (1) they are: 1. $000: $1e (indicates manufactured by atmel) 2. $001: $90 (indicates 1 kb flash memory) 3. $002: $05 (indicates attiny12 device when signature byte $001 is $90) note: 1. when both lock bits are programmed (lock mode 3), the signature bytes can not be read in the low-voltage serial mode. reading the signature bytes will return: $00, $01 and $02. calibration byte in attiny12 the attiny12 has a one-byte calibration value for the internal rc oscillator. this byte resides in the high byte of address $000 in the signature address space. during memory programming, the external programmer must read this location and program its value into a selected location in the normal flash program memory. at start-up, the user soft- ware must read this flash location and write the value to the osccal register. programming the flash and eeprom attiny11 atmel?s attiny11 offers 1k bytes of flash program memory. the attiny11 is shipped with the on-chip flash program memory array in the erased state (i.e., contents = $ff) and ready to be programmed. this device supports a high-voltage (12v) serial programming mode. only minor cur- rents (<1 ma) are drawn from the +12v pin during programming. the program memory array in the attiny11 is programmed byte-by-byte. attiny12 atmel?s attiny12 offers 1k bytes of in-system reprogrammable flash program memory and 64 bytes of in-system reprogrammable eeprom data memory. the attiny12 is shipped with the on-chip flash program and eeprom data memory arrays in the erased state (i.e., contents = $ff) and ready to be programmed. this device supports a high-voltage (12v) serial programming mode and a low-voltage serial programming mode. the +12v is used for programming enable only, and no cur- rent of significance is drawn by this pin. the low-voltage serial programming mode 48 attiny11/12 1006d?avr?07/03 provides a convenient way to download program and data into the attiny12 inside the user?s system. the program and data memory arrays in the attiny12 are programmed byte-by-byte in either programming mode. for the eeprom, an auto-erase cycle is provided within the self-timed write instruction in the low-voltage serial programming mode. attiny11/12 during programming, the supply voltage must be in accordance with table 22. table 22. supply voltage during programming high-voltage serial programming this section describes how to program and verify flash program memory, eeprom data memory (attiny12), lock bits and fuse bits in the attiny11/12. figure 27. high-voltage serial programming part low-voltage serial programming high-voltage serial programming attiny11l not applicable 4.5 - 5.5v attiny11 not applicable 4.5 - 5.5v attiny12v 2.2 - 5.5v 4.5 - 5.5v attiny12l 2.7 - 5.5v 4.5 - 5.5v attiny12 4.0 - 5.5v 4.5 - 5.5v pb5 (reset) pb3 (xtal1) gnd vcc pb2 pb1 pb0 serial data output serial instr. input serial data input serial clock input 11.5 - 12.5v 4.5 - 5.5v attiny 49 attiny11/12 1006d?avr?07/03 high-voltage serial programming algorithm to program and verify the attiny11/12 in the high-voltage serial programming mode, the following sequence is recommended (see instruction formats in table 23): 1. power-up sequence: apply 4.5 - 5.5v between v cc and gnd. set pb5 and pb0 to ?0? and wait at least 100 ns. toggle pb3 at least four times with minimum 100 ns pulse-width. set pb3 to ?0?. wait at least 100 ns. apply 12v to pb5 and wait at least 100 ns before changing pb0. wait 8 s before giving any instructions. 2. the flash array is programmed one byte at a time by supplying first the address, then the low and high data byte. the write instruction is self-timed, wait until the pb2 (rdy/bsy ) pin goes high. 3. the eeprom array (attiny12 only) is programmed one byte at a time by supply- ing first the address, then the data byte. the write instruction is self-timed, wait until the pb2 (rdy/bsy ) pin goes high. 4. any memory location can be verified by using the read instruction which returns the contents at the selected address at serial output pb2. 5. power-off sequence:set pb3 to ?0?. set pb5 to ?1?. tur n v cc power off. when writing or reading serial data to the attiny11/12, data is clocked on the rising edge of the serial clock, see figure 28, figure 29 and table 24 for details. 50 attiny11/12 1006d?avr?07/03 figure 28. high-voltage serial programming waveforms msb msb msb lsb lsb lsb 012345678910 serial data input pb0 serial instr. input pb1 serial data output pb2 serial clock input xtal1/pb3 table 23. high-voltage serial programming instruction set for attiny11/12 instruction instruction format operation remarks instr.1 instr.2 instr.3 instr.4 chip erase pb0 pb1 pb2 0_1000_0000_00 0_0100_1100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_0100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_1100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0100_1100_00 x_xxxx_xxxx_xx wait after instr.4 until pb2 goes high for the chip erase cycle to finish. write flash high and low address pb0 pb1 pb2 0_0001_0000_00 0_0100_1100_00 x_xxxx_xxxx_xx 0_0000_000 a _00 0_0001_1100_00 x_xxxx_xxxx_xx 0_ bbbb _ bbbb _00 0_0000_1100_00 x_xxxx_xxxx_xx repeat instr.2 for a new 256 byte page. repeat instr.3 for each new address. write flash low byte pb0 pb1 pb2 0_ i i i i _ i i i i _00 0_0010_1100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_0100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_1100_00 0_0000_0000_00 wait after instr.3 until pb2 goes high. repeat instr.1, instr. 2 and instr.3 for each new address. write flash high byte pb0 pb1 pb2 0_ i i i i _ i i i i _00 0_0011_1100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0111_0100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0111_1100_00 0_0000_0000_00 wait after instr.3 until pb2 goes high. repeat instr.1, instr. 2 and instr.3 for each new address. read flash high and low address pb0 pb1 pb2 0_0000_0010_00 0_0100_1100_00 x_xxxx_xxxx_xx 0_0000_000 a _00 0_0001_1100_00 x_xxxx_xxxx_xx 0_ bbbb _ bbbb _00 0_0000_1100_00 x_xxxx_xxxx_xx repeat instr.2 and instr.3 for each new address. read flash low byte pb0 pb1 pb2 0_0000_0000_00 0_0110_1000_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_1100_00 o _ oooo _ ooo x_xx repeat instr.1 and instr.2 for each new address. read flash high byte pb0 pb1 pb2 0_0000_0000_00 0_0111_1000_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0111_1100_00 o _ oooo _ ooo x_xx repeat instr.1 and instr.2 for each new address. write eeprom low address (attiny12) pb0 pb1 pb2 0_0001_0001_00 0_0100_1100_00 x_xxxx_xxxx_xx 0_00 bb _ bbbb _00 0_0000_1100_00 x_xxxx_xxxx_xx repeat instr.2 for each new address. write eeprom byte (attiny12) pb0 pb1 pb2 0_ i i i i _ i i i i _00 0_0010_1100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_0100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_1100_00 0_0000_0000_00 wait after instr.3 until pb2 goes high read eeprom low address (attiny12) pb0 pb1 pb2 0_0000_0011_00 0_0100_1100_00 x_xxxx_xxxx_xx 0_00 bb _ bbbb _00 0_0000_1100_00 x_xxxx_xxxx_xx repeat instr.2 for each new address. 51 attiny11/12 1006d?avr?07/03 note: a = address high bits b = address low bits i = data in o = data out x = don?t care 1 = lock bit1 2 = lock bit2 3 = cksel0 fuse 4 = cksel1 fuse 5 = cksel2 fuse 9 , 6 = rstdisbl fuse 7 = fstrt fuse 8 = cksel3 fuse a = spien fuse b = boden fuse c = bodlevel fuse read eeprom byte (attiny12) pb0 pb1 pb2 0_0000_0000_00 0_0110_1000_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_1100_00 o _ oooo _ ooo x_xx repeat instr.2 for each new address write fuse bits (attiny11) pb0 pb1 pb2 0_0100_0000_00 0_0100_1100_00 x_xxxx_xxxx_xx 0_000 7 _ 6543 _00 0_0010_1100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_0100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_1100_00 x_xxxx_xxxx_xx wait t wlwh_pfb after instr.3 for the write fuse bits cycle to finish. write 7 - 3 = ?0? to program the fuse bit. write fuse bits (attiny12) pb0 pb1 pb2 0_0100_0000_00 0_0100_1100_00 x_xxxx_xxxx_xx 0_ cba9 _ 8543 _00 0_0010_1100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_0100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_1100_00 x_xxxx_xxxx_xx wait after instr.4 until pb2 goes high. write c - a , 9, 8, 5 - 3 = ?0? to program the fuse bit. write lock bits pb0 pb1 pb2 0_0010_0000_00 0_0100_1100_00 x_xxxx_xxxx_xx 0_0000_0210_00 0_0010_1100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_0100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_1100_00 0_0000_0000_00 wait after instr.4 until pb2 goes high. write 2 , 1 = ?0? to program the lock bit. read fuse bits (attiny11) pb0 pb1 pb2 0_0000_0100_00 0_0100_1100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_1000_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_1100_00 x_xx 76 _ 543 x_xx reading 7 - 3 = ?0? means the fuse bit is programmed. read fuse bits (attiny12) pb0 pb1 pb2 0_0000_0100_00 0_0100_1100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_1000_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_1100_00 c _ ba98 _ 543 x_xx reading c - a , 9 , 8 , 5 - 3 = ?0? means the fuse bit is programmed. read lock bits pb0 pb1 pb2 0_0000_0100_00 0_0100_1100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0111_1000_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0111_1100_00 x_xxxx_ 21 xx_xx reading 2 , 1 = ?0? means the lock bit is programmed. read signature bytes pb0 pb1 pb2 0_0000_1000_00 0_0100_1100_00 x_xxxx_xxxx_xx 0_0000_00 bb _00 0_0000_1100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_1000_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_1100_00 o _ oooo _ ooo x_xx repeat instr.2 - instr.4 for each signature byte address read calibration byte (attiny12) pb0 pb1 pb2 0_0000_1000_00 0_0100_1100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0000_1100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0111_1000_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0111_1100_00 o _ oooo _ ooo x_xx table 23. high-voltage serial programming instruction set for attiny11/12 (continued) instruction instruction format operation remarks instr.1 instr.2 instr.3 instr.4 52 attiny11/12 1006d?avr?07/03 high-voltage serial programming characteristics figure 29. high-voltage serial programming timing low-voltage serial downloading (attiny12 only) both the program and data memory arrays can be programmed using the spi bus while reset is pulled to gnd. the serial interface consists of pins sck, mosi (input) and miso (output), see figure 30. after reset is set low, the programming enable instruc- tion needs to be executed first before program/erase instructions can be executed. figure 30. serial programming and verify table 24. high-voltage serial programming characteristics t a = 25 c 10%, v cc = 5.0v 10% (unless otherwise noted) symbol parameter min typ max units t shsl sci (pb3) pulse width high 100 ns t slsh sci (pb3) pulse width low 100 ns t ivsh sdi (pb0), sii (pb1) valid to sci (pb3) high 50 ns t shix sdi (pb0), sii (pb1) hold after sci (pb3) high 50 ns t shov sci (pb3) high to sdo (pb2) valid 10 16 32 ns t wlwh_pfb wait after instr. 3 for write fuse bits 1.7 2.5 3.4 ms sdi (pb0), sii (pb1) sdo (pb2) sci (pb3) t ivsh t shsl t slsh t shix t shov pb5 (reset) vcc pb2 pb1 pb0 sck miso mosi 2.2 - 5.5v gnd attiny12 gnd 53 attiny11/12 1006d?avr?07/03 if the chip erase command in low-voltage serial programming is executed only once, one data byte may be written to the flash after erase. using the following algorithm guar- antees that the flash will be erased: execute a chip erase command write $ff to address $00 in the flash execute a second chip erase command for the eeprom, an auto-erase cycle is provided within the self-timed write instruction and there is no need to first execute the chip erase instruction. the chip erase instruc- tion turns the content of every memory location in both the program and eeprom arrays into $ff. the program and eeprom memory arrays have separate address spaces: $0000 to $01ff for program memory and $000 to $03f for eeprom memory. the device can be clocked by any clock option during low-voltage serial programming. the minimum low and high periods for the serial clock (sck) input are defined as follows: low: > 2 mcu clock cycles high: > 2 mcu clock cycles low-voltage serial programming algorithm when writing serial data to the attiny12, data is clocked on the rising edge of sck. when reading data from the attiny12, data is clocked on the falling edge of sck. see figure 31, figure 32 and table 26 for timing details. to program and verify the attiny12 in the serial programming mode, the following sequence is recommended (see 4 byte instruction formats in table 25 ): 1. power-up sequence: apply power between vcc and gnd while reset and sck are set to ?0?. in accor- dance with the setting of cksel fuses, apply a crystal/resonator, external clock or rc network, or let the device run on the internal rc oscillator. in some systems, the programmer can not guarantee that sck is held low during power-up. in this case, reset must be given a positive pulse of at least two mcu cycles duration after sck has been set to ?0?. 2. wait for at least 20 ms and enable serial programming by sending the program- ming enable serial instruction to the mosi (pb0) pin. 3. the serial programming instructions will not work if the communication is out of synchronization. when in sync, the second byte ($53) will echo back when issu- ing the third byte of the programming enable instruction. whether the echo is correct or not, all 4 bytes of the instruction must be transmitted. if the $53 did not echo back, give sck a positive pulse and issue a new programming enable instruction. if the $53 is not seen within 32 attempts, there is no functional device connected. 4. if a chip erase is performed (must be done to erase the flash), wait t wd_erase after the instruction, give reset a positive pulse, and start over from step 2. see table 27 on page 56 for t wd_erase value. 5. the flash or eeprom array is programmed one byte at a time by supplying the address and data together with the appropriate write instruction. an eeprom memory location is first automatically erased before new data is written. use data polling to detect when the next byte in the flash or eeprom can be writ- ten. if polling is not used, wait t wd_flash or t wd_eeprom before transmitting the 54 attiny11/12 1006d?avr?07/03 next instruction. see table 28 on page 56 for t wd_flash and t wd_eeprom values. in an erased device, no $ffs in the data file(s) needs to be programmed. 6. any memory location can be verified by using the read instruction which returns the content at the selected address at the serial output miso (pb1) pin. 7. at the end of the programming session, reset can be set high to commence normal operation. 8. power-off sequence (if needed): set xtal1 to ?0? (if external clocking is used). set reset to ?1?. turn v cc power off. data polling when a byte is being programmed into the flash or eeprom, reading the address location being programmed will give the value $ff. at the time the device is ready for a new byte, the programmed value will read correctly. this is used to determine when the next byte can be written. this will not work for the value $ff, so when programming this value, the user will have to wait for at least t wd_flash or t wd_eeprom before programming the next byte. as a chip-erased device contains $ff in all locations, programming of addresses that are meant to contain $ff can be skipped. this does not apply if the eeprom is reprogrammed without chip-erasing the device. in that case, data polling cannot be used for the value $ff, and the user will have to wait at least t wd_eeprom before programming the next byte. see table 28 for t wd_flash and t wd_eeprom values. figure 31. low-voltage serial programming waveforms msb msb lsb lsb serial clock input pb2(sck) serial data input pb0(mosi) serial data output pb1(miso) 55 attiny11/12 1006d?avr?07/03 note: a = address high bits b = address low bits h = 0 - low byte, 1 - high byte o = data out i = data in x = don?t care 1 = lock bit 1 2 = lock bit 2 3 = cksel0 fuse 4 = cksel1 fuse 5 = cksel2 fuse 6 = cksel3 fuse 7 = rstdisbl fuse 8 = spien fuse 9 = boden fuse a = bodlevel fuse note: 1. the signature bytes are not readable in lock mode 3, i.e. both lock bits programmed. table 25. low-voltage serial programming instruction set instruction instruction format operation byte 1 byte 2 byte 3 byte4 programming enable 1010 1100 0101 0011 xxxx xxxx xxxx xxxx enable serial programming while reset is low. chip erase 1010 1100 100x xxxx xxxx xxxx xxxx xxxx chip erase flash and eeprom memory arrays. read program memory 0010 h 000 xxxx xxx a bbbb bbbb oooo oooo read h (high or low) data o from program memory at word address a : b . write program memory 0100 h 000 xxxx xxx a bbbb bbbb iiii iiii write h (high or low) data i to program memory at word address a : b . read eeprom memory 1010 0000 xxxx xxxx xx bb bbbb oooo oooo read data o from eeprom memory at address b . write eeprom memory 1100 0000 xxxx xxxx xx bb bbbb iiii iiii write data i to eeprom memory at address b . write lock bits 1010 1100 1111 1 21 1 xxxx xxxx xxxx xxxx write lock bits. set bits 1,2 = ?0? to program lock bits. read lock bits 0101 1000 xxxx xxxx xxxx xxxx xxxx x 21 x read lock bits. ?0? = programmed, ?1? = unprogrammed. read signature bytes 0011 0000 xxxx xxxx 0000 00 bb oooo oooo read signature byte o at address b . (1) read calibration byte 0011 1000 xxxx xxxx 0000 0000 oooo oooo write fuse bits 1010 1100 101x xxxx xxxx xxxx a987 6543 set bits a , 9 - 3 = ?0? to program, ?1? to unprogram. read fuse bits 0101 0000 xxxx xxxx xxxx xxxx a987 6543 read fuse bits. ?0? = programmed, ?1? = unprogrammed. 56 attiny11/12 1006d?avr?07/03 low-voltage serial programming characteristics figure 32. low-voltage serial programming timing table 26. low-voltage serial programming characteristics t a = -40 c to 85 c, v cc = 2.2 - 5.5v (unless otherwise noted) symbol parameter min typ max units 1/t clcl oscillator frequency (v cc = 2.2 - 2.7v) 0 1 mhz t clcl oscillator period (v cc = 2.2 - 2.7v) 1000 ns 1/t clcl oscillator frequency (v cc = 2.7 - 4.0v) 0 4 mhz t clcl oscillator period (v cc = 2.7 - 4.0v) 250 ns 1/t clcl oscillator frequency (v cc = 4.0 - 5.5v) 0 8 mhz t clcl oscillator period (v cc = 4.0 - 5.5v) 125 ns t shsl sck pulse width high 2 t clcl ns t slsh sck pulse width low 2 t clcl ns t ovsh mosi setup to sck high t clcl ns t shox mosi hold after sck high 2 t clcl ns t sliv sck low to miso valid 10 16 32 ns table 27. minimum wait delay after the chip erase instruction symbol minimum wait delay t wd_erase 6.8 ms table 28. minimum wait delay after writing a flash or eeprom location symbol minimum wait delay t wd_flash 3.4 ms t wd_eeprom 6.8 ms mosi miso sck t ovsh t shsl t slsh t shox t sliv 57 attiny11/12 1006d?avr?07/03 electrical characteristics absolute maximum ratings operating temperature .................................. -55 c to +125 c *notice: stresses beyond those ratings listed under ?absolute maximum ratings? may cause perma- nent damage to the device. this is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rat- ing conditions for extended periods may affect device reliability. storage temperature ..................................... -65c to +150c voltage on any pin except reset with respect to ground ................................-1.0v to v cc +0.5v voltage on reset with respect to ground......-1.0v to +13.0v maximum operating voltage ............................................ 6.0v dc current per i/o pin ............................................... 40.0 ma dc current v cc and gnd pins................................ 100.0 ma dc characteristics ? preliminary data t a = -40 c to 85 c, v cc = 2.7v to 5.5v for attiny11, v cc = 1.8v to 5.5v for attiny12 (unless otherwise noted) symbol parameter condition min typ max units v il input low voltage except (xtal) -0.5 0.3 v cc (1) v v il1 input low voltage xtal -0.5 0.1 v cc (1) v v ih input high voltage except (xtal, reset ) 0.6 v cc (2) v cc + 0.5 v v ih1 input high voltage xtal 0.7 v cc (2) v cc + 0.5 v v ih2 input high voltage reset 0.85 v cc (2) v cc + 0.5 v v ol output low voltage (3) port b i ol = 20 ma, v cc = 5v i ol = 10 ma, v cc = 3v 0.6 0.5 v v v ol output low voltage pb5 (attiny12) i ol = 12 ma, v cc = 5v i ol = 6 ma, v cc = 3v 0.6 0.5 v v v oh output high voltage (4) port b i oh = -3 ma, v cc = 5v i oh = -1.5 ma, v cc = 3v 4.3 2.3 v v i il input leakage current i/o pin v cc = 5.5v, pin low (absolute value) 8.0 a i ih input leakage current i/o pin v cc = 5.5v, pin high (absolute value) 8.0 a r i/o i/o pin pull-up 35 122 k ? 58 attiny11/12 1006d?avr?07/03 notes: 1. ?max? means the highest value where the pin is guaranteed to be read as low. 2. ?min? means the lowest value where the pin is guaranteed to be read as high. 3. although each i/o port can sink more than the test conditions (20 ma at v cc = 5v, 10 ma at v cc = 3v) under steady state conditions (non-transient), the following must be observed: 1] the sum of all i ol , for all ports, should not exceed 100 ma. if i ol exceeds the test condition, v ol may exceed the related specification. pins are not guaranteed to sink current greater than the listed test conditions. 4. although each i/o port can source more t han the test conditions (3 ma at v cc = 5v, 1.5 ma at v cc = 3v) under steady state conditions (non-transient), the following must be observed: 1] the sum of all i oh , for all ports, should not exceed 100 ma. if i oh exceeds the test condition, v oh may exceed the related specification. pins are not guaranteed to source current greater than the listed test condition. 5. minimum v cc for power-down is 1.5v. (on attiny12: only with bod disabled) i cc power supply current active 1 mhz, v cc = 3v (attiny12v) 1.0 ma active 2 mhz, v cc = 3v (attiny11l) 2.0 ma active 4 mhz, v cc = 3v (attiny12l) 2.5 ma active 6 mhz, v cc = 5v (attiny11) 10 ma active 8 mhz, v cc = 5v (attiny12) 10 ma idle 1 mhz, v cc = 3v (attiny12v) 0.4 ma idle 2 mhz, v cc = 3v (attiny11l) 0.5 ma idle 4 mhz, v cc = 3v (attiny12l) 1.0 ma idle 6 mhz, v cc = 5v (attiny11) 2.0 ma idle 8 mhz, v cc = 5v (attiny12) 3.5 ma power down (5) , v cc = 3v, wdt enabled 9.0 15 a power down (5) , v cc = 3v. wdt disabled (attiny12) <1 2 a power down (5) , v cc = 3v. wdt disabled (attiny11) <1 5 a v acio analog comparator input offset voltage v cc = 5v v in = v cc /2 40 mv i aclk analog comparator input leakage current v cc = 5v v in = v cc /2 -50 50 na t acpd analog comparator propagation delay v cc = 2.7v v cc = 4.0v 750 500 ns dc characteristics ? preliminary data (continued) t a = -40 c to 85 c, v cc = 2.7v to 5.5v for attiny11, v cc = 1.8v to 5.5v for attiny12 (unless otherwise noted) symbol parameter condition min typ max units 59 attiny11/12 1006d?avr?07/03 external clock drive waveforms figure 33. external clock note: r should be in the range 3-100 k ? , and c should be at least 20 pf. the c values given in the table includes pin capacitance. this will vary with package type. external clock drive attiny11 symbol parameter v cc = 2.7v to 4.0v v cc = 4.0v to 5.5v units min max min max 1/t clcl oscillator frequency 0206mhz t clcl clock period 500 167 ns t chcx high time 200 67 ns t clcx low time 200 67 ns t clch rise time 1.6 0.5 s t chcl fall time 1.6 0.5 s external clock drive attiny12 symbol parameter v cc = 1.8v to 2.7v v cc = 2.7v to 4.0v v cc = 4.0v to 5.5v units min max min max min max 1/t clcl oscillator frequency 0 1.2 0 4 0 8 mhz t clcl clock period 833 250 125 ns t chcx high time 333 100 50 ns t clcx low time 333 100 50 ns t clch rise time 1.6 1.6 0.5 s t chcl fall time 1.6 1.6 0.5 s table 29. external rc oscillator, typical frequencies r [k ? ]c [pf] f 100 70 100 khz 31.5 20 1.0 mhz 6.5 20 4.0 mhz vil1 vih1 60 attiny11/12 1006d?avr?07/03 attiny11 typical characteristics the following charts show typical behavior. these figures are not tested during manu- facturing. all current consumption measurements are performed with all i/o pins configured as inputs and with internal pull-ups enabled. a sine wave generator with rail- to-rail output is used as clock source. the power consumption in power-down mode is independent of clock selection. the current consumption is a function of several factors such as: operating voltage, operating frequency, loading of i/o pins, switching rate of i/o pins, code executed and ambient temperature. the dominating factors are operating voltage and frequency. the current drawn from capacitive loaded pins may be estimated (for one pin) as c l * v cc *f where c l = load capacitance, v cc = operating voltage and f = average switch- ing frequency of i/o pin. the parts are characterized at frequencies higher than test limits. parts are not guaran- teed to function properly at frequencies higher than the ordering code indicates. the difference between current consumption in power-down mode with watchdog timer enabled and power-down mode with watchdog timer disabled represents the dif- ferential current drawn by the watchdog timer. figure 34. active supply current vs. frequency v cc = 5.5v v cc = 5v v cc = 4.5v t = 25 ? c a v cc = 1.8v v cc = 6v 0 2 4 6 8 10 12 14 16 18 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 active supply current vs. frequency frequency (mhz) v cc = 4v v cc = 3.6v v cc = 3.3v v cc = 3.0v v cc = 2.7v v cc = 2.4v v cc = 2.1v i (ma) cc 61 attiny11/12 1006d?avr?07/03 figure 35. active supply current vs. v cc figure 36. active supply current vs. v cc , device clocked by internal oscillator 0 1 2 3 4 5 6 7 8 9 10 2 2.5 3 3.5 4 4.5 5 5.5 6 active supply current vs. v cc frequency = 4 mhz i cc (ma) v cc (v) t = 85 ? c a t = 25 ? c a 0 1 2 3 4 5 6 2.5 3 3.5 4 4.5 5 5.5 6 active supply current vs. v cc device clocked by 1.0mhz internal rc oscillator i cc (ma) v cc (v) t = 85 ? c a t = 25 ? c a 62 attiny11/12 1006d?avr?07/03 figure 37. active supply current vs. v cc , device clocked by external 32khz crystal figure 38. idle supply current vs. frequency 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 2.5 3 3.5 4 4.5 5 5.5 6 active supply current vs. v cc device clocked by 32khz crystal i cc (ma) v cc (v) t = 85 ? c a t = 25 ? c a 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 0123456789101112131415 v cc = 6v v cc = 5.5v v cc = 5v v cc = 4.5v v cc = 4v v cc = 3.6v v cc = 3.3v v cc = 3.0v v cc = 2.7v idle supply current vs. frequency t = 25 ? c a frequency (mhz) v cc = 2.4v v cc = 2.1v v cc = 1.8v i (ma) cc 63 attiny11/12 1006d?avr?07/03 figure 39. idle supply current vs. v cc figure 40. idle supply current vs. v cc , device clocked by internal oscillator 0 1 1 2 2 3 2 2.5 3 3.5 4 4.5 5 5.5 6 t = 25 ? c a t = 85 ? c a idle supply current vs. v cc v cc (v) frequency = 4 mhz i (ma) cc 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 2.5 3 3.5 4 4.5 5 5.5 6 idle supply current vs. v cc device clocked by 1.0mhz internal rc oscillator i cc (ma) v cc (v) t = 85 ? c a t = 25 ? c a 64 attiny11/12 1006d?avr?07/03 figure 41. idle supply current vs. v cc , device clocked by external 32khz crystal figure 42. power-down supply current vs. v cc 0 5 10 15 20 25 2.5 3 3.5 4 4.5 5 5.5 6 idle supply current vs. v cc device clocked by 32khz crystal i cc ( a) v cc (v) t = 85 ? c a t = 25 ? c a 0 1 2 3 4 5 6 7 8 9 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 t = 85 ? c a t = 25 ? c a power-down supply current vs. v cc v cc (v) watchdog timer disabled i ( a) cc 65 attiny11/12 1006d?avr?07/03 figure 43. power-down supply current vs. v cc figure 44. analog comparator current vs. v cc 0 10 20 30 40 50 60 70 80 90 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 t = 85 ? c a t = 25 ? c a power-down supply current vs. v cc v cc (v) watchdog timer enabled i ( a) cc 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 analog comparator current vs. v cc v cc (v) t = 25 ? c a t = 85 ? c a i (ma) cc 66 attiny11/12 1006d?avr?07/03 analog comparator offset voltage is measured as absolute offset. figure 45. analog comparator offset voltage vs. common mode voltage figure 46. analog comparator offset voltage vs. common mode voltage 0 2 4 6 8 10 12 14 16 18 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 analog comparator offset voltage vs. v = 5v cc common mode voltage common mode voltage (v) offset voltage (mv) t = 85 ? c a t = 25 ? c a 0 2 4 6 8 10 0 0.5 1 1.5 2 2.5 3 analog comparator offset voltage vs. common mode voltage common mode voltage (v) offset voltage (mv) v = 2.7v cc t = 85 ? c a t = 25 ? c a 67 attiny11/12 1006d?avr?07/03 figure 47. analog comparator input leakage current figure 48. watchdog oscillator frequency vs. v cc 60 50 40 30 20 10 0 -10 0 0.5 1.5 1 2 2.5 3.5 3 4 4.5 5 6 6.5 7 5.5 analog comparator input leakage current t = 25 ? c a i (na) aclk v (v) in v = 6v cc 0 200 400 600 800 1000 1200 1400 1600 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 t = 85 ? c a t = 25 ? c a watchdog oscillator frequency vs. v cc v (v) cc f (khz) rc 68 attiny11/12 1006d?avr?07/03 sink and source capabilities of i/o ports are measured on one pin at a time. figure 49. pull-up resistor current vs. input voltage figure 50. pull-up resistor current vs. input voltage 0 20 40 60 80 100 120 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 pull-up resistor current vs. input voltage v = 5v cc i ( a) op v (v) op t = 85 ? c a t = 25 ? c a 0 5 10 15 20 25 30 0 0.5 1 1.5 2 2.5 3 pull-up resistor current vs. input voltage i ( a) op v (v) op v = 2.7v cc t = 85 ? c a t = 25 ? c a 69 attiny11/12 1006d?avr?07/03 figure 51. i/o pin sink current vs. output voltage figure 52. i/o pin source current vs. output voltage 0 10 20 30 40 50 60 70 80 0 0.5 1 1.5 2 2.5 3 v = 5v cc i (ma) ol v (v) ol t = 85 ? c a t = 25 ? c a i/o pin sink current vs. output voltage 0 2 4 6 8 10 12 14 16 18 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 i/o pin source current vs. output voltage v = 5v cc i (ma) oh v (v) oh t = 85 ? c a t = 25 ? c a 70 attiny11/12 1006d?avr?07/03 figure 53. i/o pin sink current vs. output voltage figure 54. i/o pin source current vs. output voltage 0 5 10 15 20 25 30 0 0.5 1 1.5 2 i (ma) ol v (v) ol t = 85 ? c a t = 25 ? c a i/o pin sink current vs. output voltage v = 2.7v cc 0 1 2 3 4 5 6 0 0.5 1 1.5 2 2.5 3 i/o pin source current vs. output voltage i (ma) oh v (v) oh t = 85 ? c a t = 25 ? c a v = 2.7v cc 71 attiny11/12 1006d?avr?07/03 figure 55. i/o pin input threshold voltage vs. v cc figure 56. i/o pin input hysteresis vs. v cc 0 0.5 1 1.5 2 2.5 2.7 4.0 5.0 threshold voltage (v) v cc i/o pin input threshold voltage vs. v cc t = 25 ? c a 0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 2.7 4.0 5.0 input hysteresis (v) v cc i/o pin input hysteresis vs. v cc t = 25 ? c a 72 attiny11/12 1006d?avr?07/03 attiny12 typical characteristics the following charts show typical behavior. these data are characterized, but not tested. all current consumption measurements are performed with all i/o pins config- ured as inputs and with internal pull-ups enabled. a sine wave generator with rail-to-rail output is used as clock source. the power consumption in power-down mode is independent of clock selection. the current consumption is a function of several factors such as: operating voltage, operating frequency, loading of i/o pins, switching rate of i/o pins, code executed and ambient temperature. the dominating factors are operating voltage and frequency. the current drawn from capacitive loaded pins may be estimated (for one pin) as c l * v cc *f where c l = load capacitance, v cc = operating voltage and f = average switch- ing frequency of i/o pin. the parts are characterized at frequencies higher than test limits. parts are not guaran- teed to function properly at frequencies higher than the ordering code indicates. the difference between current consumption in power-down mode with watchdog timer enabled and power-down mode with watchdog timer disabled represents the dif- ferential current drawn by the watchdog timer. figure 57. active supply current vs. v cc , device clocked by internal oscillator v cc (v) i cc ( m ) active supply current vs. v cc device clocked by 1.2mhz internal rc oscillator 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 t = 85 ? c a t = 25 ? c a 73 attiny11/12 1006d?avr?07/03 figure 58. active supply current vs. v cc , device clocked by external 32khz crystal figure 59. idle supply current vs. v cc , device clocked by internal oscillator 0 20 40 60 80 100 120 140 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 v cc (v) i cc (?) t = 25 ? c a t = 85 ? c a active supply current vs. v cc device clocked by 32khz crystal v cc (v) idle supply current vs. v cc i cc ( m ) device clocked by 1.2mhz internal rc oscillator 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 t = 25 ? c a t = 85 ? c a 74 attiny11/12 1006d?avr?07/03 figure 60. idle supply current vs. v cc , device clocked by external 32khz crystal analog comparator offset voltage is measured as absolute offset. figure 61. analog comparator offset voltage vs. common mode voltage v cc (v) idle supply current vs. v cc 0 5 10 15 20 25 30 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 t = 85 ? c a t = 25 ? c a i cc (?) device clocked by 32khz crystal 0 2 4 6 8 10 12 14 16 18 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 analog comparator offset voltage vs. v = 5v cc common mode voltage common mode voltage (v) offset voltage (mv) t = 85 ? c a t = 25 ? c a 75 attiny11/12 1006d?avr?07/03 figure 62. analog comparator offset voltage vs. common mode voltage figure 63. analog comparator input leakage current 0 2 4 6 8 10 0 0.5 1 1.5 2 2.5 3 analog comparator offset voltage vs. common mode voltage common mode voltage (v) offset voltage (mv) v = 2.7v cc t = 85 ? c a t = 25 ? c a 60 50 40 30 20 10 0 -10 0 0.5 1.5 1 2 2.5 3.5 3 4 4.5 5 6 6.5 7 5.5 analog comparator input leakage current t = 25 ? c a i (na) aclk v (v) in v = 6v cc 76 attiny11/12 1006d?avr?07/03 figure 64. calibrated rc oscillator frequency vs. v cc figure 65. watchdog oscillator frequency vs. v cc calibrated rc oscillator frequency vs. v cc (v) 1.06 1.08 1.1 1.12 1.14 1.16 1.18 1.2 1.22 2 2.5 3 3.5 4 4.5 5 5.5 6 t = 85 ? c a t = 25 ? c a t = 45 ? c a t = 70 ? c a operating voltage f rc (mhz) 0 200 400 600 800 1000 1200 1400 1600 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 t = 85 ? c a t = 25 ? c a watchdog oscillator frequency vs. v cc v (v) cc f (khz) rc 77 attiny11/12 1006d?avr?07/03 sink and source capabilities of i/o ports are measured on one pin at a time. figure 66. pull-up resistor current vs. input voltage (v cc = 5v) figure 67. pull-up resistor current vs. input voltage (v cc = 2.7v) 0 20 40 60 80 100 120 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 i ( a) op v (v) op t = 85 ? c a t = 25 ? c a 0 5 10 15 20 25 30 0 0.5 1 1.5 2 2.5 3 i ( a) op v (v) op t = 85 ? c a t = 25 ? c a 78 attiny11/12 1006d?avr?07/03 figure 68. i/o pin sink current vs. output voltage (v cc = 5v) figure 69. i/o pin source current vs. output voltage (v cc = 5v) 0 10 20 30 40 50 60 70 0 0.5 1 1.5 2 2.5 3 i (ma) ol v (v) ol t = 85 ? c a t = 25 ? c a 0 2 4 6 8 10 12 14 16 18 20 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 i (ma) oh v (v) oh t = 85 ? c a t = 25 ? c a 79 attiny11/12 1006d?avr?07/03 figure 70. i/o pin sink current vs. output voltage (v cc = 2.7v) figure 71. i/o pin source current vs. output voltage (v cc = 2.7v) 0 5 10 15 20 25 0 0.5 1 1.5 2 i (ma) ol v (v) ol t = 85 ? c a t = 25 ? c a 0 1 2 3 4 5 6 0 0.5 1 1.5 2 2.5 3 i (ma) oh v (v) oh t = 85 ? c a t = 25 ? c a 80 attiny11/12 1006d?avr?07/03 figure 72. i/o pin input threshold voltage vs. v cc (t a = 25 c) figure 73. i/o pin input hysteresis vs. v cc (t a = 25 c) 0 0.5 1 1.5 2 2.5 2.7 4.0 5.0 threshold voltage (v) v cc 0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 2.7 4.0 5.0 input hysteresis (v) v cc 81 attiny11/12 1006d?avr?07/03 notes: 1. for compatibility with future devices, reserved bits shou ld be written to zero if accessed. reserved i/o memory address es should never be written. 2. some of the status flags are cleared by writing a logical one to them. note that the cbi and sbi instructions will operate on all bits in the i/o register, writing a one back into any flag read as set, thus clearing the flag. the cbi and sbi instruction s work with registers $00 to $1f only. register summary attiny11 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page $3f sreg i t h s v n z c page 14 $3e reserved $3d reserved $3c reserved $3b gimsk - int0 pcie - - - - - page 25 $3a gifr -intf0pcif - - - - - page 26 $39 timsk - - - - - -toie0 - page 26 $38 tifr - - - - - -tov0 - page 27 $37 reserved $36 reserved $35 mcucr - -sesm - - isc01 isc00 page 29 $34 mcusr - - - - - - extrf porf page 23 $33 tccr0 - - - - - cs02 cs01 cs00 page 34 $32 tcnt0 timer/counter0 (8 bit) page 35 $31 reserved $30 reserved ... reserved $22 reserved $21 wdtcr - - - wdtoe wde wdp2 wdp1 wdp0 page 36 $20 reserved $1f reserved $1e reserved $1d reserved $1c reserved $1b reserved $1a reserved $19 reserved $18 portb - - - portb4 portb3 portb2 portb1 portb0 page 44 $17 ddrb - - - ddb4 ddb3 ddb2 ddb1 ddb0 page 44 $16 pinb - - pinb5 pinb4 pinb3 pinb2 pinb1 pinb0 page 44 $15 reserved ... reserved $0a reserved $09 reserved $08 acsr acd - aco aci acie - acis1 acis0 page 41 ? reserved $00 reserved 82 attiny11/12 1006d?avr?07/03 note: 1. for compatibility with future devices, reserved bits should be written to zero if accessed. reserved i/o memory addresse s should never be written. 2. some of the status flags are cleared by writing a logical one to them. note that the cbi and sbi instructions will operate on all bits in the i/o register, writing a one back into any flag read as set, thus clearing the flag. the cbi and sbi instruction s work with registers $00 to $1f only. register summary attiny12 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page $3f sreg i t h s v n z c page 14 $3e reserved $3d reserved $3c reserved $3b gimsk - int0 pcie - - - - - page 25 $3a gifr -intf0pcif - - - - - page 26 $39 timsk - - - - - -toie0 - page 26 $38 tifr - - - - - -tov0 - page 27 $37 reserved $36 reserved $35 mcucr - pud se sm - - isc01 isc00 page 29 $34 mcusr - - - - wdrf borf extrf porf page 24 $33 tccr0 - - - - - cs02 cs01 cs00 page 34 $32 tcnt0 timer/counter0 (8 bit) page 35 $31 osccal oscillator calibration register page 32 $30 reserved ... reserved $22 reserved $21 wdtcr - - - wdtoe wde wdp2 wdp1 wdp0 page 36 $20 reserved $1f reserved $1e eear - - eeprom address register page 38 $1d eedr eeprom data register page 38 $1c eecr - - - - eerie eemwe eewe eere page 38 $1b reserved $1a reserved $19 reserved $18 portb - - - portb4 portb3 portb2 portb1 portb0 page 44 $17 ddrb - - ddb5 ddb4 ddb3 ddb2 ddb1 ddb0 page 44 $16 pinb - - pinb5 pinb4 pinb3 pinb2 pinb1 pinb0 page 44 $15 reserved ... reserved $0a reserved $09 reserved $08 acsr acd ainbg aco aci acie - acis1 acis0 page 41 ... reserved $00 reserved 83 attiny11/12 1006d?avr?07/03 instruction set summary mnemonics operands description operation flags #clocks arithmetic and logic instructions add rd, rr add two registers rd rd + rr z,c,n,v,h 1 adc rd, rr add with carry two registers rd rd + rr + c z,c,n,v,h 1 sub rd, rr subtract two registers rd rd - rr z,c,n,v,h 1 subi rd, k subtract constant from register rd rd - k z,c,n,v,h 1 sbc rd, rr subtract with carry two registers rd rd - rr - c z,c,n,v,h 1 sbci rd, k subtract with carry constant from reg. rd rd - k - c z,c,n,v,h 1 and rd, rr logical and registers rd rd ? rr z,n,v 1 andi rd, k logical and register and constant rd rd ? k z,n,v 1 or rd, rr logical or registers rd rd v rr z,n,v 1 ori rd, k logical or register and constant rd rd v k z,n,v 1 eor rd, rr exclusive or registers rd rd rr z,n,v 1 com rd one?s complement rd $ff - rd z,c,n,v 1 neg rd two?s complement rd $00 - rd z,c,n,v,h 1 sbr rd,k set bit(s) in register rd rd v k z,n,v 1 cbr rd,k clear bit(s) in register rd rd ? (ffh - k) z,n,v 1 inc rd increment rd rd + 1 z,n,v 1 dec rd decrement rd rd - 1 z,n,v 1 tst rd test for zero or minus rd rd ? rd z,n,v 1 clr rd clear register rd rd rd z,n,v 1 ser rd set register rd $ff none 1 branch instructions rjmp k relative jump pc pc + k + 1 none 2 rcall k relative subroutine call pc pc + k + 1 none 3 ret subroutine return pc stack none 4 reti interrupt return pc stack i 4 cpse rd,rr compare, skip if equal if (rd = rr) pc pc + 2 or 3 none 1/2 cp rd,rr compare rd - rr z, n,v,c,h 1 cpc rd,rr compare with carry rd - rr - c z, n,v,c,h 1 cpi rd,k compare register with immediate rd - k z, n,v,c,h 1 sbrc rr, b skip if bit in register cleared if (rr(b)=0) pc pc + 2 or 3 none 1/2 sbrs rr, b skip if bit in register is set if (rr(b)=1) pc pc + 2 or 3 none 1/2 sbic p, b skip if bit in i/o register cleared if (p(b)=0) pc pc + 2 or 3 none 1/2 sbis p, b skip if bit in i/o register is set if (p(b)=1) pc pc + 2 or 3 none 1/2 brbs s, k branch if status flag set if (sreg(s) = 1) then pc pc + k + 1 none 1/2 brbc s, k branch if status flag cleared if (sreg(s) = 0) then pc pc + k + 1 none 1/2 breq k branch if equal if (z = 1) then pc pc + k + 1 none 1/2 brne k branch if not equal if (z = 0) then pc pc + k + 1 none 1/2 brcs k branch if carry set if (c = 1) then pc pc + k + 1 none 1/2 brcc k branch if carry cleared if (c = 0) then pc pc + k + 1 none 1/2 brsh k branch if same or higher if (c = 0) then pc pc + k + 1 none 1/2 brlo k branch if lower if (c = 1) then pc pc + k + 1 none 1/2 brmi k branch if minus if (n = 1) then pc pc + k + 1 none 1/2 brpl k branch if plus if (n = 0) then pc pc + k + 1 none 1/2 brge k branch if greater or equal, signed if (n v= 0) then pc pc + k + 1 none 1/2 brlt k branch if less than zero, signed if (n v= 1) then pc pc + k + 1 none 1/2 brhs k branch if half carry flag set if (h = 1) then pc pc + k + 1 none 1/2 brhc k branch if half carry flag cleared if (h = 0) then pc pc + k + 1 none 1/2 brts k branch if t flag set if (t = 1) then pc pc + k + 1 none 1/2 brtc k branch if t flag cleared if (t = 0) then pc pc + k + 1 none 1/2 brvs k branch if overflow flag is set if (v = 1) then pc pc + k + 1 none 1/2 brvc k branch if overflow flag is cleared if (v = 0) then pc pc + k + 1 none 1/2 brie k branch if interrupt enabled if ( i = 1) then pc pc + k + 1 none 1/2 brid k branch if interrupt disabled if ( i = 0) then pc pc + k + 1 none 1/2 84 attiny11/12 1006d?avr?07/03 data transfer instructions ld rd,z load register indirect rd (z) none 2 st z,rr store register indirect (z) rr none 2 mov rd, rr move between registers rd rr none 1 ldi rd, k load immediate rd knone1 in rd, p in port rd pnone1 out p, rr out port p rr none 1 lpm load program memory r0 (z) none 3 bit and bit-test instructions sbi p,b set bit in i/o register i/o(p,b) 1none2 cbi p,b clear bit in i/o register i/o(p,b) 0none2 lsl rd logical shift left rd(n+1) rd(n), rd(0) 0 z,c,n,v 1 lsr rd logical shift right rd(n) rd(n+1), rd(7) 0 z,c,n,v 1 rol rd rotate left through carry rd(0) c, rd(n+1) rd(n), c rd(7) z,c,n,v 1 ror rd rotate right through carry rd(7) c, rd(n) rd(n+1), c rd(0) z,c,n,v 1 asr rd arithmetic shift right rd(n) rd(n+1), n = 0..6 z,c,n,v 1 swap rd swap nibbles rd(3..0) rd(7..4), rd(7..4) rd(3..0) none 1 bset s flag set sreg(s) 1sreg(s)1 bclr s flag clear sreg(s) 0 sreg(s) 1 bst rr, b bit store from register to t t rr(b) t 1 bld rd, b bit load from t to register rd(b) tnone1 sec set carry c 1c1 clc clear carry c 0 c 1 sen set negative flag n 1n1 cln clear negative flag n 0 n 1 sez set zero flag z 1z1 clz clear zero flag z 0 z 1 sei global interrupt enable i 1i1 cli global interrupt disable i 0 i 1 ses set signed test flag s 1s1 cls clear signed test flag s 0 s 1 sev set twos complement overflow v 1v1 clv clear twos complement overflow v 0 v 1 set set t in sreg t 1t1 clt clear t in sreg t 0 t 1 seh set half carry flag in sreg h 1h1 clh clear half carry flag in sreg h 0 h 1 nop no operation none 1 sleep sleep (see specific descr. for sleep function) none 1 wdr watch dog reset (see specific descr. for wdr/timer) none 1 instruction set summary (continued) mnemonics operands description operation flags #clocks 85 attiny11/12 1006d?avr?07/03 note: the speed grade refers to maximum clock rate when using an external crystal or external clock drive. the internal rc oscil lator has the same nominal clock frequency for all speed grades. ordering information power supply speed (mhz) ordering code package operation range 2.7 - 5.5v 2 attiny11l-2pc attiny11l-2sc 8p3 8s2 commercial (0 c to 70 c) attiny11l-2pi attiny11l-2si 8p3 8s2 industrial (-40 c to 85 c) 4.0 - 5.5v 6 attiny11-6pc at t i n y 1 1 - 6 s c 8p3 8s2 commercial (0 c to 70 c) at t i n y 1 1 - 6 p i at t i n y 1 1 - 6 s i 8p3 8s2 industrial (-40 c to 85 c) 1.8 - 5.5v 1.2 attiny12v-1pc attiny12v-1sc 8p3 8s2 commercial (0 c to 70 c) attiny12v-1pi attiny12v-1si 8p3 8s2 industrial (-40 c to 85 c) 2.7 - 5.5v 4 attiny12l-4pc ATTINY12L-4SC 8p3 8s2 commercial (0 c to 70 c) attiny12l-4pi attiny12l-4si 8p3 8s2 industrial (-40 c to 85 c) 4.0 - 5.5v 8 attiny12-8pc at t i n y 1 2 - 8 s c 8p3 8s2 commercial (0 c to 70 c) at t i n y 1 2 - 8 p i at t i n y 1 2 - 8 s i 8p3 8s2 industrial (-40 c to 85 c) package type 8p3 8-lead, 0.300" wide, plastic dual inline package (pdip) 8s2 8-lead, 0.200" wide, plastic gull-wing small outline (eiaj soic) 86 attiny11/12 1006d?avr?07/03 packaging information 8p3 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 8p3 , 8-lead, 0.300" wide body, plastic dual in-line package (pdip) 01/09/02 8p3 b d d1 e e1 e l b2 b a2 a 1 n ea c b3 4 plcs top view side view end view common dimensions (unit of measure = inches) symbol min nom max note notes: 1. this drawing is for general information only; refer to jedec drawing ms-001, variation ba for additional information. 2. dimensions a and l are measured with the package seated in jedec seating plane gauge gs-3. 3. d, d1 and e1 dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.010 inch. 4. e and ea measured with the leads constrained to be perpendicular to datum. 5. pointed or rounded lead tips are preferred to ease insertion. 6. b2 and b3 maximum dimensions do not include dambar protrusions. dambar protrusions shall not exceed 0.010 (0.25 mm). a 0.210 2 a2 0.115 0.130 0.195 b 0.014 0.018 0.022 5 b2 0.045 0.060 0.070 6 b3 0.030 0.039 0.045 6 c 0.008 0.010 0.014 d 0.355 0.365 0.400 3 d1 0.005 3 e 0.300 0.310 0.325 4 e1 0.240 0.250 0.280 3 e 0.100 bsc ea 0.300 bsc 4 l 0.115 0.130 0.150 2 87 attiny11/12 1006d?avr?07/03 8s2 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 8s2 , 8-lead, 0.209" body, plastic small outline package (eiaj) 5/2/02 8s2 b top view side view end view h 1 n c e a b l a1 e d common dimensions (unit of measure = mm) symbol min nom max note notes: 1. this drawing is for general information only; refer to eiaj drawing edr-7320 for additional information. 2. mismatch of the upper and lower dies and resin burrs aren't included. 3. it is recommended that upper and lower cavities be equal. if they are different, the larger dimension shall be regarded. 4. determines the true geometric position. 5. values b,c apply to pb/sn solder plated terminal. the standard thickness of the solder layer shall be 0.010 +0.010/-0.005 mm . a 1.78 2.03 a1 0.05 0.33 b 0.35 0.51 5 c 0.18 0.25 5 d 5.13 5.38 e 5.13 5.41 2, 3 h 7.62 8.38 l 0.51 0.89 e 1.27 bsc 4 88 attiny11/12 1006d?avr?07/03 data sheet change log for attiny11/12 please note that the referring page numbers in this section are referred to this docu- ment. the referring revision in this section are referring to the document revision. changes from rev. 1006c-09/01 to rev. 1006d-07/03 1. updated v bot values in table 8 on page 19. i attiny11/12 1006d?avr?07/03 table of contents features................................................................................................. 1 pin configuration.................................................................................. 1 description ............................................................................................ 2 attiny11 block diagram ....................................................................................... 2 attiny12 block diagram ....................................................................................... 4 pin descriptions.................................................................................................... 5 clock options ....................................................................................................... 5 architectural overview......................................................................... 8 general-purpose register file.............................................................................. 9 alu ? arithmetic logic unit................................................................................ 10 flash program memory ...................................................................................... 10 program and data addressing modes................................................................ 10 subroutine and interrupt hardware stack .......................................................... 12 eeprom data memory...................................................................................... 13 memory access and instruction execution timing ............................................. 13 i/o memory ......................................................................................................... 14 reset and interrupt handling.............................................................................. 15 attiny12 internal voltage reference.................................................................. 24 interrupt handling ............................................................................................... 25 sleep modes for the attiny11 ............................................................................ 31 sleep modes for the attiny12 ............................................................................ 31 attiny12 calibrated internal rc oscillator ......................................................... 32 timer/counter0 ................................................................................... 33 timer/counter prescaler..................................................................................... 33 watchdog timer.................................................................................. 36 attiny12 eeprom read/write access............................................. 38 prevent eeprom corruption ............................................................................. 40 analog comparator ............................................................................ 41 i/o port b ............................................................................................. 43 memory programming........................................................................ 46 program (and data) memory lock bits .............................................................. 46 fuse bits in attiny11.......................................................................................... 46 fuse bits in attiny12.......................................................................................... 46 signature bytes .................................................................................................. 47 calibration byte in attiny12 ............................................................................... 47 programming the flash and eeprom............................................................... 47 high-voltage serial programming....................................................................... 48 ii attiny11/12 1006d?avr?07/03 high-voltage serial programming algorithm....................................................... 49 high-voltage serial programming characteristics .............................................. 52 low-voltage serial downloading (attiny12 only) ............................................... 52 low-voltage serial programming characteristics ............................................... 56 electrical characteristics................................................................... 57 absolute maximum ratings ................................................................................ 57 dc characteristics ? preliminary data ............................................................... 57 external clock drive waveforms ........................................................................ 59 external clock drive attiny11 ............................................................................ 59 external clock drive attiny12 ............................................................................ 59 attiny11 typical characteristics ........................................................................ 60 attiny12 typical characteristics ........................................................................ 72 register summary attiny11 .............................................................. 81 register summary attiny12 .............................................................. 82 instruction set summary ................................................................... 83 ordering information.......................................................................... 85 packaging information ....................................................................... 86 8p3 ..................................................................................................................... 86 8s2 ..................................................................................................................... 87 data sheet change log for chip number ........................................ 88 changes from rev. 1006c-09/01 to rev. 1006d-07/03..................................... 88 table of contents .................................................................................. i printed on recycled paper. disclaimer: atmel corporation makes no warranty for the use of its products , other than those expressly contained in the company?s standar d warranty which is detailed in atmel?s terms and conditions located on the company?s web site. the company assumes no responsibi lity for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time wi thout notice, and does not make any commitment to update the information contained herein. no licenses to patents or other intellectual property of atmel are granted by the company in connection with the sale of atmel produc ts, expressly or by implication. atmel?s products are not aut horized for use as critical components in life support devices or systems. atmel corporation atmel operations 2325 orchard parkway san jose, ca 95131 tel: 1(408) 441-0311 fax: 1(408) 487-2600 regional headquarters europe atmel sarl route des arsenaux 41 case postale 80 ch-1705 fribourg switzerland tel: (41) 26-426-5555 fax: (41) 26-426-5500 asia room 1219 chinachem golden plaza 77 mody road tsimshatsui east kowloon hong kong tel: (852) 2721-9778 fax: (852) 2722-1369 japan 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel: (81) 3-3523-3551 fax: (81) 3-3523-7581 memory 2325 orchard parkway san jose, ca 95131 tel: 1(408) 441-0311 fax: 1(408) 436-4314 microcontrollers 2325 orchard parkway san jose, ca 95131 tel: 1(408) 441-0311 fax: 1(408) 436-4314 la chantrerie bp 70602 44306 nantes cedex 3, france tel: (33) 2-40-18-18-18 fax: (33) 2-40-18-19-60 asic/assp/smart cards zone industrielle 13106 rousset cedex, france tel: (33) 4-42-53-60-00 fax: (33) 4-42-53-60-01 1150 east cheyenne mtn. blvd. colorado springs, co 80906 tel: 1(719) 576-3300 fax: 1(719) 540-1759 scottish enterprise technology park maxwell building east kilbride g75 0qr, scotland tel: (44) 1355-803-000 fax: (44) 1355-242-743 rf/automotive theresienstrasse 2 postfach 3535 74025 heilbronn, germany tel: (49) 71-31-67-0 fax: (49) 71-31-67-2340 1150 east cheyenne mtn. blvd. colorado springs, co 80906 tel: 1(719) 576-3300 fax: 1(719) 540-1759 biometrics/imaging/hi-rel mpu/ high speed converters/rf datacom avenue de rochepleine bp 123 38521 saint-egreve cedex, france tel: (33) 4-76-58-30-00 fax: (33) 4-76-58-34-80 e-mail literature@atmel.com web site http://www.atmel.com 1006d?avr?07/03 0m ? atmel corporation 2003 . all rights reserved. atmel ? and combinations thereof, avr ? and avr studio ? are the registered trademarks of atmel corporation or its subsidiaries. other terms and product names may be the trademarks of others. |
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